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ahb-lite

Here are 5 public repositories matching this topic...

chipsalliance / Cores-SweRV

SweRV EH1 core

fpga processor riscv rtl risc risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design swerv swerv-eh1

Updated Jan 27, 2022
SystemVerilog

chipsalliance / Cores-SweRV-EL2

SweRV EL2 Core

fpga processor riscv rtl risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design swerv swerv-el2 el2

Updated May 21, 2021
SystemVerilog

Lampro-Mellon / Quasar

Quasar 2.0: Chisel equivalent of SweRV-EL2

scala processor chisel riscv rtl chisel3 open-source-hardware verilator asic-verification axi4 ahb-lite asic-design swerv swerv-el2

Updated Apr 13, 2021
Scala

TILhub / AMBA-3-AHB-Lite-Protocol

This Repo contains SystemC for testBench for AMBA® 3 AHB-Lite Protocol

arm cplusplus protocol emulation stl systemc lite testbenches testbench amba ahb-lite

Updated Jul 11, 2018
C++

WajahatRiaz / AHB-Lite-Protocol-Verification

Attempt to develop a verification IP and plan for a bus functional model of ARM based AMBA 3 AHB-LITE Protocol. Implemented object oriented programming techniques in SysteVerilog.

arm systemverilog ahb-lite systemverilog-developer systemverilog-test-bench

Updated Apr 25, 2022
SystemVerilog

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