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fpga-programming
Here are 55 public repositories matching this topic...
A curated collection of technical documentation for Arcades, Handhelds, Consoles, Computers and MCU’s.
video-games
documentation
arm
fpga
mips
pcb
arcade
wiring
diagrams
retrogaming
schematics
mcu
user-manual
system-on-chip
eletronics
manuals
datasheets
service-manual
fpga-programming
vintage-computers
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Mar 20, 2020
Intermediate Language (IL) for Hardware Accelerator Generators
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Nov 15, 2020 - Rust
Program Lattice MachXO2/3 with CircuitPython
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Sep 13, 2019 - Python
Collection of my projects that was made as a part of Warsaw University FPGA course
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Feb 5, 2019 - Verilog
Příklady ke knize Data, čipy, procesory
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Oct 10, 2020 - VHDL
A command line utility to generate bitstreams and various programming files easily for PLDs
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Jun 30, 2020 - Python
Implemented an ultrasonic sensor to measure and visualize distances on the FPGA 7-seg Display and LEDs.
vhdl
ultrasonic-sensor
xilinx-fpga
7segment
vhdl-modules
vhdl-code
nexys4ddr
parking-sensor
fpga-programming
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Dec 5, 2019 - VHDL
Impement a simple stopwatch on an FPGA. There is an added goal of making as many modules paramterized as possible and sticking to structural code as much as possible.
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Jul 26, 2020 - Verilog
Arduino Library for programming MachXO2/XO3 devices
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Sep 26, 2019 - C++
A Pseudo-Random Noise Sequence Generator VHDL implementation to synthesize on a Zync FPGA for the Digital Systems Design course of University of Pisa, 2019.
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Aug 14, 2019 - VHDL
VHDL game that displays incremental random sequences on a LED Matrix by creating a finite state machine and implementing RAM and ROM models.
vhdl
simon-game
finite-state-machine
xilinx
led-matrix-displays
vhdl-modules
vhdl-code
nexys4ddr
fpga-programming
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Jul 18, 2019 - VHDL
SPI module for Nexys 4 Artix-7 FPGA Trainer Board
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May 4, 2020 - Verilog
Verilog sources for FPGA Zybo board implementing vision algorithms.
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Jul 1, 2018 - VHDL
Source Code of Yocto Layer for accessing FPGA Manager of the Intel (ALTERA) Arria 10 SX SoCFPGA
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May 15, 2020 - C++
VHDL code written in ModelSim for Encryption and Decryption of data (binary messages) using Simplified Data Encryption Standard.
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Jun 3, 2020 - VHDL
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Feb 9, 2017 - Verilog
My experiments with Nexys4 DDR Artix-7 FPGA Board
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Oct 1, 2020 - Verilog
IIR Filter for audio application
fpga
filter
vhdl
audio-applications
digital-signals
xilinx
digital-signal-processing
iir
filtering
xilinx-fpga
audio-processing
filter-design
vhdl-modules
vhdl-code
digital-signal-filtering
vhdl-examples
iir-filter
xilinx-zynq
fpga-programming
digital-signal
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May 28, 2019 - VHDL
Yocto Project Layer for accessing FPGA Manager of the Intel (ALTERA) Cyclone V and Arria 10 SoCFPGA
fpga
intel
yocto-layer
altera
fpga-soc-linux
cyclone-v
yocto-project
socfpga
intel-fpga
fpga-programming
arria10
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Jul 9, 2020 - BitBake
Spartan 6 Lx16 Xilinx FPGA board implementing retro 80's 90's machines
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Dec 3, 2019 - VHDL
Converts any file to coe format.
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Mar 29, 2018
Simple RTL model for Interger Numbers Calculation using RAM and 7 Segment Display.
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Jul 14, 2019 - VHDL
Digital Systems Course Project: Fake Currency Detection in Verilog using Basys3 FPGA and MATLAB
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Sep 30, 2020 - VHDL
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I feel like I might be doing something incredibly dumb, but I was just trying to write a program (compiling to FuTIL) and found myself confused about the appropriate width for memory index subscripts. This program type-checks and compiles just fine:
And just for completeness, this program, of course, emits the "zero-padding not supp