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trains
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Timer 4 is the 40 bit debug timer (as described under section 18.1.3). It's similar to Timers 1-3, albeit without as much "customization" options.
It should be fairly easy to implement:
- Modify the current
timerdevice to use a internalu64counter for time-keeping - Create a "wrapper" device which masks masks out any timer registers unavailable on Timer 4
- Update the
Ts7200Busstruc
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