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SystemVerilog expressions evaluator has strange signed results in bit vector fields (resets->value,mask)
bug
#35
opened Dec 31, 2019 by
mwsealey
Kactus doesn't correctly deal with XML namespaces
enhancement
feature request
#31
opened Aug 31, 2019 by
andreasWallner
Verilog generator loses existing module implementation
Plugin
bug
#29
opened Jun 25, 2019 by
epekkar
0 of 2
Verilog generation uses default values instead of expressions/parameter name in component instantiation.
#21
opened Dec 28, 2018 by
ithinuel
memoryMaps visualizer slows down on large models
bug
enhancement
#15
opened Oct 11, 2018 by
DanChianucci
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