openhwgroup / cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
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The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
OpenTitan: Open source silicon root of trust
4 stage, in-order, secure RISC-V core based on the CV32E40P
Pipelines the AXI path with FIFOs
AXI X-Bar
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
AXI Dual-Clock FIFO for clock domain crossings (CDC)
AXI to Peripheral Interconnect
Private instruction cache for PULP cluster
Peripheral Bus to AXI adapter
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
Generic Register Interface (contains various adatpers)
IPs for control-plane integration of Hardware Processing Engines (HWPEs) within a PULP system