EttusResearch / uhd
The USRP™ Hardware Driver Repository
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The USRP™ Hardware Driver Repository
Verilog AXI components for FPGA implementation
Learning how to make a RISC-V
HDL libraries and projects
RTL, Cmodel, and testbench for NVDLA
Documenting the Lattice ECP5 bit-stream format.
The Ultra-Low Power RISC-V Core
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
OpenROAD's unified application implementing an RTL-to-GDS Flow
PicoRV32 - A Size-Optimized RISC-V CPU
SERV - The SErial RISC-V CPU