OpenHW Group

Repositories

• core-v-verif

  Functional verification project for the CORE-V family of RISC-V cores.
  Assembly 61 101 37 4 Updated May 13, 2021

• cva6

  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

  asic cpu fpga riscv questasim verilator systemverilog-hdl
  SystemVerilog 297 1,178 97 (1 issue needs help) 16 Updated May 12, 2021

• cv32e40x

  4 stage, in-order, compute RISC-V core based on the CV32E40P
  SystemVerilog 8 15 0 0 Updated May 12, 2021

• core-v-docs

  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  Python 44 63 0 5 Updated May 10, 2021

• core-v-sw

  Main Repo for the OpenHW Group Software Task Group
  EPL-2.0 11 1 1 1 Updated May 10, 2021

• cv32e40p

  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

  riscv riscv32imfc
  SystemVerilog 203 475 48 (2 issues need help) 7 Updated May 8, 2021

• cv32e40s

  4 stage, in-order, secure RISC-V core based on the CV32E40P
  SystemVerilog 6 4 1 0 Updated May 7, 2021

• core-v-mcu

  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

  microcontroller riscv systemverilog openhwgroup
  SystemVerilog 8 17 28 3 Updated May 7, 2021

• infra

  Issues related to the OpenHW Group infra (GtHub, Mattermost, ...)
  0 0 1 0 Updated May 4, 2021

• openhwgroup.org

  OpenHW Group is a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate in the development of open-source cores, related IP, tools and software. OpenHW provides an infrastructure for hosting high quality open-source HW developments in line with industry best practi…

  hugo webdev
  HTML EPL-2.0 7 9 1 0 Updated Apr 30, 2021

• corev-binutils-gdb
  C 5 2 1 3 Updated Apr 29, 2021

• pulp_soc

  Forked from pulp-platform/pulp_soc
  SystemVerilog 38 0 0 0 Updated Apr 7, 2021

• corev-llvm-project
  C++ 2 1 1 3 Updated Apr 7, 2021

• core-v-ide-cdt
  Java EPL-2.0 3 5 7 2 Updated Mar 31, 2021

• core-v-cores

  CORE-V Family of RISC-V Cores
  2 21 0 0 Updated Mar 29, 2021

• force-riscv

  Instruction Set Generator initially contributed by Futurewei
  C++ 21 67 2 0 Updated Mar 19, 2021

• riscv-ovpsim-corev
  1 2 0 0 Updated Mar 16, 2021

• timer_unit

  Forked from pulp-platform/timer_unit
  SystemVerilog 3 0 1 1 Updated Feb 18, 2021

• core-v-freertos
  C Apache-2.0 0 0 0 0 Updated Feb 17, 2021

• core-v-freertos-kernel
  C 0 0 0 0 Updated Feb 17, 2021

• osdforum.org

  The Open Source Developer Forum is a workshop that brings open source software and hardware (chips, boards and systems) developers together to collaborate and learn.

  hugo webdev
  HTML EPL-2.0 4 0 0 0 Updated Jan 23, 2021

• corev-elf-psabi-doc
  0 0 0 0 Updated Nov 13, 2020

• riscv_vm

  Instructions to import Ubuntu guest Virtual Machine for RISC-V development for the VEGA board
  Shell Apache-2.0 2 9 9 0 Updated Nov 12, 2020

• apb_interrupt_cntrl

  Forked from pulp-platform/apb_interrupt_cntrl

  Small and simple APB interrupt controller
  SystemVerilog 4 0 0 0 Updated Nov 10, 2020

• corev-gcc
  5 3 0 0 Updated Sep 14, 2020

• OpenHW-Admin-Tools

  This is a private repo with tools and 'how-to' documentation for OpenHW Staff to use. We may make this repo public at some point.
  EPL-2.0 0 0 0 1 Updated May 9, 2020

• core-v-trace
  0 0 0 0 Updated Apr 22, 2020