lowRISC / opentitan
OpenTitan: Open source silicon root of trust
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OpenTitan: Open source silicon root of trust
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Wavious DDR (WDDR) Physical interface (PHY) Hardware
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
AXI Adapter(s) for RISC-V Atomic Operations
APB Timer Unit
[UNRELEASED] FP div/sqrt unit for transprecision
IP Blocks to Support Design, Prototyping, and Verification of PULP on FPGAs
open-source Ethenet media access controller for Ariane on Genesys-2
Generic Register Interface (contains various adatpers)
SweRV EH1 core