wishbone

A small, light weight, RISC CPU soft core

Bus bridges and other odds and ends

A simple, basic, formally verified UART controller

A utility for Composing FPGA designs from Peripherals

An Open Source configuration of the Arty platform

SD-Card controller, using a SPI interface that is (optionally) shared

A wishbone controlled scope for FPGA's

Simple UART controller for FPGA written in VHDL

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

CMod-S6 SoC

A collection of debugging busses developed and presented at zipcpu.com

A wishbone controlled FM transmitter hack

🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).

A caravan equipped with API for creating bus protocols in Chisel with ease.

RISC-V Ibex core with Wishbone B4 interface

rv32i/rv32im/rv32imc for iCE40. Wishbone interface.

HDL components to build a customized Wishbone crossbar switch

In this repository, it is presented the whole design of a functional RISC processor. Therefore, the design of every functional block (arithmetic and control units among others) is written in Verilog and the verification of every single block is provided.

Wishbone to ICAPE interface conversion

Direct Access Memory for MPSoC

Example Risc-V SoC with VexRiscv, custom peripherals and bare metal firmware

Multi-Port RAM for Instruction & Data for MPSoC

Message Passing Interface for MPSoC

Single-Port RAM for Instruction & Data for MPSoC

Universal Asynchronous Receiver-Transmitter for MPSoC

Master Slave Interface for MPSoC

同济大学CS《计算机系统实验》实验二TongJi University CS computer system experiment assignment 2

General Purpose Input Output for MPSoC

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