lowRISC / opentitan
OpenTitan: Open source silicon root of trust
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OpenTitan: Open source silicon root of trust
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
AXI X-Bar
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
RISC-V Debug Support for our PULP RISC-V Cores
[UNRELEASED] FP div/sqrt unit for transprecision
Pipelines the AXI path with FIFOs
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
Control interface for FLL
APB Timer Unit
IP Blocks to Support Design, Prototyping, and Verification of PULP on FPGAs
Generic Register Interface (contains various adatpers)
open-source Ethenet media access controller for Ariane on Genesys-2
Simple single-port AXI memory interface
AXI Dual-Clock FIFO for clock domain crossings (CDC)
IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
AXI Adapter(s) for RISC-V Atomic Operations