BrunoLevy / learn-fpga
Learning FPGA, yosys, nextpnr, and RISC-V
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Learning FPGA, yosys, nextpnr, and RISC-V
HDL libraries and projects
OpenROAD's unified application implementing an RTL-to-GDS Flow
Wraps the NVDLA project for Chipyard integration
PicoRV32 - A Size-Optimized RISC-V CPU
Must-have verilog systemverilog modules
RISC-V System on Chip Template Based on the picorv32 Processor
The USRP™ Hardware Driver Repository
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.
Another tiny RISC-V implementation
Verilog AXI components for FPGA implementation