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ghdl

Here are 49 public repositories matching this topic...

ghdl / ghdl

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Revisit CLI syntax

9

eine commented Apr 9, 2020

Currently, the architecture of the CLI is based on (sub)commands and options. Commands are expected to be provided as the first argument, and do effectively decide which feature is to be used. OTOH, options provide parameters to the commands. However, there is no syntactical difference, as both commands and options start with -- or -i. As a result, we rely on properly formating --help and on

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Good First Issue

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FST and real data type

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The testsuite should not depend on the docs.

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olofk / edalize

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An abstraction library for interfacing EDA tools

Updated Jun 30, 2021
Python

suoto / hdl_checker

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Repurposing existing HDL tools to help writing better code

python vim language-server vhdl issue-tracker standalone verilog xilinx syntax-checker systemverilog trademarks hdl modelsim questasim ghdl xilinx-vivado lsp-server coc-nvim vim-ale vivado-simulator mentor-msim hdl-checker emacs-lsp

Updated Jun 5, 2021
Python

jakubcabal / spi-fpga

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SPI master and SPI slave for FPGA written in VHDL

fpga controller vhdl accelerometer spi ghdl spi-master spi-slave cyc1000 spi-loopback spi-controller

Updated Apr 24, 2021
VHDL

Paebbels / JSON-for-VHDL

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A JSON library implemented in VHDL.

parser json fpga simulation vhdl xilinx synthesis lattice fileformat modelsim questasim ghdl

Updated Aug 3, 2020
VHDL

jakubcabal / uart-for-fpga

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Simple UART controller for FPGA written in VHDL

fpga simulation controller vhdl uart ghdl wishbone uart-controller wishbone-bus cyc1000 uart-loopback

Updated Apr 20, 2021
VHDL

tmeissner / psl_with_ghdl

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Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)

vhdl assertions ghdl formal-verification yosys psl symbiyosys functional-coverage

Updated Feb 20, 2021
VHDL

ghdl / docker

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Scripts to build and use docker images including GHDL

dockerfiles hardware ci simulation vhdl actions verilog synthesis icestorm gtkwave ghdl testbench vunit yosys openocd pnr nextpnr prjtrellis

Updated Apr 27, 2021
Shell

tmeissner / formal_hw_verification

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Trying to verify Verilog/VHDL designs with formal methods and tools

vhdl verilog systemverilog ghdl formal-verification yosys psl symbiyosys

Updated Mar 13, 2021
VHDL

dbhi / vboard

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Virtual development board for HDL design

vhdl verilog hdl ghdl cosim vpi verilator fli vhpidirect

Updated Jun 15, 2021
VHDL

PyFPGA / pyfpga

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Improve the Vivado block design example

rodrigomelo9 opened Feb 11, 2021

enhancement good first issue

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Verify windows support

4

tmeissner / libvhdl

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Library of reusable VHDL components

coverage fpga vhdl verification assertions testbenches ghdl formal-verification osvvm psl

Updated Aug 13, 2020
VHDL

tmeissner / cryptocores

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cryptography ip-cores in vhdl / verilog

cryptography fpga vhdl verilog testbenches ghdl

Updated Feb 20, 2021
VHDL

rodrigomelo9 / verifying-foss-hdl-synthesizers

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a project to check the FOSS synthesizers against vendors EDA tools

vivado ise ghdl yosys iverilog verilator quartus pyfpga ghdl-yosys-plugin foss-synthesizers

Updated Sep 26, 2020
Makefile

dominiksalvet / risc63

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💻 Custom 64-bit pipelined RISC processor.

Updated Jan 6, 2021
VHDL

taneroksuz / riscv-fpu

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IEEE 754 standard floating point unit fpu single double precision verilog vhdl riscv

fpga vhdl verification systemverilog floating-point fma systemc ghdl division multiplier nan verilator fpu sqrt single-precision-floating-point double-precisions riscv-fpu

Updated Apr 24, 2021
VHDL

marph91 / icestick-remote

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Remote control in VHDL, which fits on a Lattice icestick.

fpga hardware vhdl ghdl ice40 icestick

Updated Jan 13, 2021
VHDL

PLC2 / Solution-StopWatch

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Professional VHDL Class Solution - StopWatch

training simulation stopwatch vhdl class rtl xilinx synthesis vivado ghdl plc2

Updated Oct 9, 2020
VHDL

vhdl-docker-template

YoussefRaafatNasry / vhdl-docker-template

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Template for creating VHDL project using docker

docker vscode gtkwave ghdl vuint

Updated Mar 20, 2020
VHDL

nobodywasishere / upduino-projects

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Various VHDL projects I've worked on for the Upduino v2.0 and v3.0

toolchain vhdl icestorm ghdl upduino upduino2 ghdl-yosys-plugin

Updated Dec 24, 2020
VHDL

umarcor / SIEAV

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Co-simulation and behavioural verification with VHDL, C/C++ and Python/m

matlab octave gtkwave ghdl vunit cosim co-simulation

Updated Jun 5, 2021
VHDL

dbhi / containers

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Containerized open and free development tools for Dynamic Binary Hardware Injection (DBHI)

docker arm zynq octave pynq gtkwave ghdl vunit dynamorio multiarch podman

Updated Jun 28, 2021
Dockerfile

qnighy / ghdl-hello

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GHDL Sample Program & Makefile

Updated Dec 17, 2014
VHDL

vscode-ghdl-interface

johannesbonk / vscode-ghdl-interface

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A tool to invoke ghdl/gtkwave functions, including error highlighting

vscode vscode-extension gtkwave ghdl vscode-plugin ghdl-interface

Updated Jun 11, 2021
JavaScript

dominiksalvet / bachelor-thesis

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📖 Bakalářská práce o návrhu procesoru RISC63.

Updated Sep 27, 2020
TeX

Kazhuu / vhdl-examples

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VHDL examples for a different kind of topics

vim examples example vhdl example-project modelsim ghdl example-code vim-hdl example-codes hdlcc

Updated Jun 4, 2020
VHDL

eine / ghdl-packaging

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Sources for package management systems to build GHDL

debian archlinux fedora deb rpm pkgbuild msys2 ghdl mingw32 mingw64

Updated Jul 25, 2020
Shell

baptistepetit / cordic

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A Naive CORDIC implementation

algorithm hardware ghdl cordic ci-environment

Updated Apr 17, 2021
VHDL

marph91 / icestick-uart

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Lightweight UART implementation in VHDL for the lattice icestick

fpga hardware vhdl uart ghdl yosys ice40 icestick

Updated May 14, 2021
VHDL

RubioHaro / VHDL

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vhdl galaxy ghdl escom sistemas-digitales

Updated Jun 19, 2021
VHDL

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