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mips

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mipt-mips
pavelkryukov
pavelkryukov commented Mar 18, 2020

Some RISC-V instructions perform writes to 2 destinations, either 2 register or register or program counter. In cases if the source of one sub-operation matches a destination of another one, the order of result output is important. The examples are jalr and instruction operating with CSRs:

riscv-software-src/riscv-tests#258
riscv-software-src/riscv-tests#263

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