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chipsalliance / Cores-SweRV

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SweRV EH1 core

fpga processor riscv rtl risc risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design swerv swerv-eh1

Updated Mar 12, 2021
SystemVerilog

mrLSD / riscv-fs

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F# RISC-V Instruction Set formal specification

library cpu fsharp fs riscv isa risc-v risc-processor riscv32 riscv64 riscv-simulator riscv-emulator

Updated Nov 20, 2020
F#

chipsalliance / Cores-SweRV-EL2

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SweRV EL2 Core

fpga processor riscv rtl risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design swerv swerv-el2 el2

Updated May 21, 2021
SystemVerilog

skyzh / RISCV-Simulator

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💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visualization. Project report available.

cmake cpu pipeline cpp riscv gtest computer-architecture speculation branch-prediction riscv32 riscv-simulator riscv-emulator tomasulo-algorithm

Updated Jul 2, 2020
C++

drom / awesome-riscv

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Open

Add more RISC-V projects

12

drom commented Oct 6, 2019

In AlphaBetical order, Please.

tommythorn / yarvi

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Yet Another RISC-V Implementation

fpga riscv verilog fpga-soc risc-v riscv32

Updated Apr 11, 2021
Verilog

ultraembedded / exactstep

Sponsor Star

Instruction accurate instruction set simulator for RISC-V, MIPS and ARM-v6m

mips armv6 risc-v instruction-set-simulator mips32 riscv32 riscv64 riscv-simulator

Updated Jun 5, 2021
C++

Domipheus / ArtyS7-RPU-SoC

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Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.

c fpga firmware vhdl riscv spi vivado apache2 hdmi fpga-soc risc-v xilinx-vivado dvid riscv32

Updated Oct 5, 2020
VHDL

LekKit / RVVM

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RISC-V Virtual Machine

c emulator vm virtual-machine emulation riscv risc emulators risc-v riscv32 riscv-emulator instruction-decoding rvvm

Updated Jul 4, 2021
C

pulp-platform / hero-sdk

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HERO Software Development Kit

openmp parallel-computing embedded-systems riscv armv7 heterogeneous-parallel-programming fpga-soc-linux pulp risc-v open-source-hardware heterogeneous-systems riscv32

Updated Oct 11, 2019
Shell

marlls1989 / arv

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ARV: Asynchronous RISC-V Go High-level Functional Model

go golang hardware asynchronous processor riscv hdl risc-v riscv32 qdi

Updated May 18, 2021
Go

jasonlin316 / RISC-V-CPU

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A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.

processor vector verilog chip risc-v riscv32 gate-level place-and-route tape-out

Updated Dec 2, 2019
Verilog

scarv / scarv-cpu

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SCARV: a side-channel hardened RISC-V platform

open-source cryptography cpu crypto riscv verilog research-project mit-license ise formal-verification yosys instruction-set-architecture verilator riscv32 xcrypto

Updated Apr 30, 2021
Verilog

franzflasch / riscv_em

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Simple risc-v emulator, able to run linux, written in C.

c emulator embedded-systems riscv risc-v embedded-c uclinux riscv32 riscv-linux rv32 riscv64 riscv-emulator rv64 riscv-em

Updated May 4, 2021
C

chillancezen / Zelda.RISCV.Emulator

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A System Level RISCV32 Emulator Over x86_64: capable of booting RISCV Linux

virtualization riscv risc-v riscv32 riscv-emulator dynamic-binary-translation riscv-isa

Updated Nov 13, 2020
C

physical-computation / sunflower-embedded-system-emulator

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Sunflower Full-System Hardware Emulator and Physical System Simulator for Sensor-Driven Systems. Built-in architecture modeling of Hitachi SH (j-core), RISC-V, and more.

processor-architecture simulator embedded-systems j-core riscv cross-compiler network-simulator emulators processor-simulator superh hitachi riscv32 battery-simulator power-simulator riscv-sim riscv-simulator riscv-emulator

Updated Mar 4, 2021
C

princeofpython / Computer-Architecture

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Detailed and step by step implementation of RISC-V CPU from scratch using Verilog. This work is part of my academic course EE2003, Introduction to Computer Organisation in IIT Madras.

cpu processor verilog pipelining alu risc-v riscv32