analogdevicesinc / hdl
HDL libraries and projects
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HDL libraries and projects
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
The USRP™ Hardware Driver Repository
Verilog configurable cache
handle bus interconnection
Verilog Ethernet components for FPGA implementation
Verilog behavioral description of various memories
OpenXuantie - OpenC910 Core
Verilog AXI components for FPGA implementation
Wraps the NVDLA project for Chipyard integration
BaseJump STL: A Standard Template Library for SystemVerilog
SERV - The SErial RISC-V CPU