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OpenHW Group

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  1. cva6 Public

    The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

    SystemVerilog 1.3k 324

  2. cv32e40p Public

    CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

    SystemVerilog 503 216

  3. Functional verification project for the CORE-V family of RISC-V cores.

    Assembly 128 74

  4. Documentation for the OpenHW Group's set of CORE-V RISC-V cores

    79 51

  5. Instruction Set Generator initially contributed by Futurewei

    C++ 74 24

  6. cv32e40x Public

    4 stage, in-order, compute RISC-V core based on the CV32E40P

    SystemVerilog 44 13

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