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Language: Verilog
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ucb-bar / nvdla-wrapper
Wraps the NVDLA project for Chipyard integration
The-OpenROAD-Project / OpenROAD-flow-scripts
darklife / darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
madcowswe / ODriveHardware
High performance motor control
IObundle / iob-soc
RISC-V System on Chip Template Based on the picorv32 Processor
The-OpenROAD-Project / OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
The-OpenROAD-Project / OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow
sheldonucr / ucr-eecs168-lab
The lab schedules for EECS168 at UC Riverside
IObundle / iob-picorv32
IOb_SoC version of the Picorv32 RISC-V Verilog IP core
SI-RISCV / e200_opensource
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2