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Xtal hart
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Xtal hart

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@ustclug
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regymm/README.md

You see here a physics student goofing around.

Stats

Check out my homepage and Telegram channel !

See what I'm doing now on Trello.

Personal:

  • i7-8550u / ArchLinux / XFCE
  • C / Python / Assembly / Verilog
  • Vim / Firefox / Brave / KiCad
  • Jetson TX1 / PYNQ-Z1 / SqueakyBoard / xc7k325t / ep4ce15 / ice40hx1k / xc6slx16 / epm1270 / ad9363
  • Working on FPGA-based RISC-V hw design & osdev
  • Interested in SDR / amateur radio but don't have a license yet

In Lab(past):

  • i9-10920x / Windows 10
  • LabVIEW / Python / MATLAB
  • Altium Designer
  • VSCode

Pinned

  1. PYNQSDR Public

    PYNQ-Z1 + AD936X openwifi capable SDR platform

    15 4

  2. quasiSoC Public

    RISC-V SoC designed to be useful.

    C 12 1

  3. FPGA accelerated Path Integral Monte Carlo. Project for computational physics.

    Tcl 4 1

  4. My self-designed ZYNQ-7010 4-layer developement board.

    TeX 10 3

  5. FT2232HL JTAG & UART Downloader

    6 1

  6. SiliTune Public

    SiliTune the battery saver, undervolting tuner and CPU manager with GUI

    Python 4 2

242 contributions in the last year

Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec Jan Mon Wed Fri
Activity overview
Contributed to regymm/MyBlog, regymm/ymmepm, regymm/ungraduate-thesis and 5 other repositories

Contribution activity

January 2022

Created 3 commits in 2 repositories

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