lowRISC / opentitan
OpenTitan: Open source silicon root of trust
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OpenTitan: Open source silicon root of trust
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
IP Blocks to Support Design, Prototyping, and Verification of PULP on FPGAs
Simple single-port AXI memory interface
AXI Adapter(s) for RISC-V Atomic Operations
AXI X-Bar
RISC-V Debug Support for our PULP RISC-V Cores
handle bus interconnection
[UNRELEASED] FP div/sqrt unit for transprecision
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication