lowRISC / opentitan
OpenTitan: Open source silicon root of trust
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OpenTitan: Open source silicon root of trust
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Common SystemVerilog components
handle bus interconnection
Pipelines the AXI path with FIFOs
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
RISC-V Debug Support for our PULP RISC-V Cores
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
APB Timer Unit
open-source Ethenet media access controller for Ariane on Genesys-2
SystemVerilog modules and classes commonly used for verification
IP Blocks to Support Design, Prototyping, and Verification of PULP on FPGAs
Simple single-port AXI memory interface
AXI Adapter(s) for RISC-V Atomic Operations