analogdevicesinc / hdl
HDL libraries and projects
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HDL libraries and projects
SERV - The SErial RISC-V CPU
The USRP™ Hardware Driver Repository
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Verilog configurable cache
The Ultra-Low Power RISC-V Core
一步一步写MIPS CPU
OpenROAD's unified application implementing an RTL-to-GDS Flow
IOb_SoC version of the Picorv32 RISC-V Verilog IP core
PicoRV32 - A Size-Optimized RISC-V CPU
Verilog behavioral description of various memories
Verilog AXI components for FPGA implementation
The lab schedules for EECS168 at UC Riverside