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Here are 136 public repositories matching this topic...

olofk / edalize

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An abstraction library for interfacing EDA tools

Updated Dec 26, 2022
Python

tymonx / logic

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CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

cmake asic fpga cpp verification rtl verilog xilinx vivado systemverilog systemc unit-tests hdl modelsim uvm verilator quartus testing-rtl

Updated Nov 25, 2019
SystemVerilog

mshr-h / vscode-verilog-hdl-support

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HDL support for VS Code

ctags vscode verilog vivado systemverilog icarus-verilog modelsim hacktoberfest verilog-hdl iverilog bluespec-systemverilog verilator language-server-client systemverilog-support svls

Updated Dec 28, 2022
TypeScript

suoto / hdl_checker

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Repurposing existing HDL tools to help writing better code

Updated Mar 3, 2022
Python

loykylewong / FPGA-Application-Development-and-Simulation

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《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).

Updated Jul 10, 2022
SystemVerilog

Paebbels / JSON-for-VHDL

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A JSON library implemented in VHDL.

parser json fpga simulation vhdl xilinx synthesis lattice fileformat modelsim questasim ghdl

Updated Sep 5, 2022
VHDL

suoto / vim-hdl

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Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

productivity vhdl vim-plugins verilog xilinx syntastic syntax-checker altera systemverilog modelsim

Updated Jun 1, 2021
Python

RomeoMe5 / DDLM

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Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)

Updated Apr 26, 2022
Verilog

arthurmteodoro / install-quartus-linux

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Tutorial de instalação do Quartus Prime no Linux

fpga install-script modelsim quartus-prime quartus-linux fpga-linux

Updated Oct 16, 2019
Shell

25th-engineer / HFUT_2020_MIPS_CPU

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合肥工业大学2020年《系统硬件综合设计》（《计算机组成原理》课程设计，CPU）的代码与报告；使用Verilog实现全冒险处理机制的MIPS五段流水CPU，支持MIPS-C3的50条指令。

cpu verilog vivado modelsim mips-c3

Updated Sep 25, 2020
Assembly

MJoergen / HyperRAM

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Portable HyperRAM controller

fpga vhdl intel xilinx vivado altera lattice modelsim questasim avalon quartus artix questa hyperram

Updated Apr 19, 2022
VHDL

Moodrammer / PDP-11

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💻 Simulation for the architecture of a processor inspired by the ideas of PDP-11 processor

cpu vhdl modelsim microprogramming pdp-11 computer-arc

Updated Jan 23, 2021
VHDL

MaorAssayag / Architecture-of-CPU-projects

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VHDL , ModelSIM, Quartus, FPGA, Image Processing

fpga vhdl modelsim quartus cpu-architecture

Updated Jan 19, 2019
VHDL

esynr3z / pyhdlsim

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Example of Python and PyTest powered workflow for a HDL simulation

python asic fpga pytest rtl verilog icarus-verilog hdl modelsim system-verilog vivado-simulator

Updated Jan 17, 2021
Python

tianrenz2 / Single-Cycle-Processor

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Single-Cycle RISC-V Processor in systemverylog

verification systemverilog modelsim

Updated Apr 23, 2019
SystemVerilog

cclienti / wavedisp

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Python classes to create agnostic wave files for HDL simulator viewer

python vhdl verilog gtkwave modelsim vcd rivierapro

Updated Mar 8, 2020
Python

baleinesurseine / macOsQuartus

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Dockerize altera's Quartus ii software and run it on macOS

macos docker-container x11 modelsim xquartz quartus

Updated Apr 26, 2021
Dockerfile

DylanVanAssche / digitale-synthese

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DSSS Wireless transmit-receive system in VHDL

fpga vhdl receiver xilinx transmitter modelsim xilinx-fpga digital-systems kuleuven dsss

Updated Dec 19, 2017
VHDL

EmanOthman21 / PDP-11

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A simulation to PDP-11 microprocessor with modelsim, The design is a micro-programmed based with an average of 9 clock cycles per instruction.

vhdl assembler microprocessor alu modelsim pdp-11 pla micro-programming

Updated Jan 21, 2021
VHDL

LamaNIkesh / MScFPGAStuff

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My MSc Thesis: Low Latency Router Microarchitecture for Network-on-Chip Implemented on an FPGA

fpga verilog modelsim network-on-chip

Updated Jun 26, 2018
Verilog

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