OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
magic
asic
rtl
verilog
systemverilog
vlsi
foundry
fault
yosys
klayout
caravel
netgen
system-on-chip
openroad
openram
skywater
130nm
soc-design
rtl2gds
qflow
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Updated
Mar 20, 2022 - Verilog