softcore

A FPGA friendly 32 bit RISC-V CPU implementation

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

80186 compatible SystemVerilog CPU core and FPGA reference design

A Forth CPU and System on a Chip, based on the J1, written in VHDL

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain( chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

Mostly AVR compatible FPGA soft-core

Soft-core uController POC using the risc16f84 pic clone and sdcc c-compiler

Trying to implement a soft core SoC

Example Risc-V SoC with VexRiscv, custom peripherals and bare metal firmware

A 16 bit softcore processor implemented in VHDL

Set of basic image processing systems implemented for learning purposes.

Implementation of a soft-core CPU and an assembler

A cycle-accurate VHDL model for MCS-48 and UPI devices

A RISC/CISC 32 bit softcore processor in VHDL

Appendices for the paper "Modular transformation of embedded systems from firm-cores to soft-cores" by Ehsan Ali and Wanchalerm Pora, International Journal of Embedded Systems, 2020.

VHDL projects

a tiny risc-v (rv32i) implementation written in nsl