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openpower
Here are 23 public repositories matching this topic...
Code repo for xCAT core packages
infrastructure
cluster
provisioning
remote-execution
infrastructure-management
ipmi
openbmc
pxe
openpower
bare-metal
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Mar 25, 2022 - Perl
Testing Firmware for OpenPOWER systems
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Mar 24, 2022 - Python
The community version of HLS_BLSTM (A BLSTM FPGA accelerator of an OCR appilcation, using CAPI/SNAP))
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Sep 27, 2019 - Objective-C
OpenPOWER Host OS Test Suite
python
testing
linux
opensource
test-runner
test-automation
python3
test-framework
kvm
powervm
openpower
powerpc
avocado-framework
guest-vm
guest-tests
avocado-tests
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Nov 12, 2021 - Python
Infrastructure as Code for OpenPOWER Host OS
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Aug 3, 2018 - Groovy
OpenPOWER Foundation General Information & Repository Listing
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Mar 25, 2022
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Feb 22, 2020 - Verilog
The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue *** MIRROR ***
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Mar 25, 2022 - Verilog
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Currently we don't reset registers or we use
:=initalisers when defining signals.This works ok in FPGAs and ghdl sim but sucks for ASIC and gate level sim as it causes a lot of X state propagation issues.
Scrub all of the code to add resets to register state.