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Efficient Trace, Supervisor Binary Interface, Unified Extensible Firmware Interface, and Zmmul Multiply-Only Extension Accelerate Embedded- and Large-System Design. Six Additional Specifications Already In the Pipeline As Development Extends Into Vertical…
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RISC-V: The Free and Open RISC Instruction Set Architecture
RISC-V is the free and open ISA
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RISC-V International is a non-profit organization supporting the free and open RISC instruction set architecture and extensions. We enable open community collaboration, technology advancements in the RISC-V ecosystem, and visibility of RISC-V successes.
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RISC-V Blog
ROMA development platform features forthcoming quad-core RISC-V processor for fastest, seamless RISC-V software development experience. DeepComputing and Xcalibyte today opened pre-orders for the industry’s first native RISC-V development laptop. The…
YADRO and Syntacore hosted the first ever engineering hackathon for students in Russia. The event was organized in association with National Research University of Electronic Technology (MIET) and took place…
In the News
Espressif has announced its first RISC-V chip — and the industry's first, it claims — to offer dual-band Wi-Fi 6 and Bluetooth Low Energy (BLE) connectivity: the ESP32-C5. Following on…
Breker Verification Systems, the leading provider of advanced test content synthesis solutions, including RISC-V Cache Coherency and other SoC integration Verification Intellectual Property (VIP) in the "TrekApps" family, today joined…
Announcements
Efficient Trace, Supervisor Binary Interface, Unified Extensible Firmware Interface, and Zmmul Multiply-Only Extension Accelerate Embedded- and Large-System Design. Six Additional Specifications Already In the Pipeline As Development Extends Into Vertical…
RISC-V welcomes Intel to the Board of Directors to collaborate on RISC-V IP and contribute engineering expertise to accelerate RISC-V software development ZURICH – February 7, 2022 – RISC-V International,…
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