RISC-V

Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.

Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.

请问可以直接training tmfile出来吗? 因为tengine-convert-tool covert 会有error

tengine-lite library version: 1.4-dev
Get input tensor failed

或是有例子能training出下面tmfile 呢?
![Screenshot from 2021-05-27 07-01-46](https://user-images.githubusercontent.com/40915044/11

If this is not the case a page fault should be generated. Right now we generate an instruction access fault.

https://github.com/pulp-platform/ariane/blob/ad70ce1f30dad539e5a365ffe71a02aaf20b397e/src/load_store_unit.sv#L339

About this question, here is a unified reply.

We need to see this place where one is the definition and load the configuration.

https://github.com/sipeed/MaixPy/blob/master/components/micropython/port/builtin_py/board.py

If you don't provide the configuration, you won't get the concrete variable.

If it is SIPEED published hardware, the appropriate configuration is provided here.

htt

Type of issue: feature request

Impact: new rtl

Development Phase: request

Other information
As the vector extension proposal is near stable and the necessary things is defined in the rocket chip repo I think now the vector e

Is your feature request related to a problem? Please describe.
Yes

Describe the solution you'd like
Please add STM32 G491 series

Describe alternatives you've considered
Running probe-run --list-chips does not include any STM32 G491 entries

Additional context
Thanks!

edit: This line is similar to the G431. I was able to flash and get code running with no evident is

I have just recently installed RARS as a replacement for RVS and there doesn't seem to be the ability to display the hex and decimal value at the same time.

If there is already a way to do this apologies for the issue.

attached is a screenshot of how RVS handles it

This is not strictly related to CV32E40P as the problem seems to be in fpnew, but did anybody verify the operation of CV32E40P with fpnew in verilator?

There is a coding-style in fpnew, which prevents verilator to work. But even if this problem is solved, the simulation is not running due to a deadlog in the div_sqrt unit. The same code runs with Questa/Modelsim without problems!?

It is hard

RISC-V

Here are 524 public repositories matching this topic...

Tencent / ncnn

capstone-engine / capstone

unicorn-engine / unicorn

OAID / Tengine

rcore-os / rCore

chipsalliance / rocket-chip

SpinalHDL / VexRiscv

openhwgroup / cva6

darklife / darkriscv

sipeed / MaixPy

riscv-boom / riscv-boom

stnolting / neorv32

ucb-bar / chipyard

probe-rs / probe-rs

TheThirdOne / rars

openhwgroup / cv32e40p

chipsalliance / Cores-SweRV

michaeljclark / rv8

syntacore / scr1

rustsbi / rustsbi

riscv-mcu / e203_hbirdv2

sergeykhbr / riscv_vhdl

pulp-platform / pulp-dronet

takahirox / riscv-rust

d0iasm / rvemu

jserv / shecc

andrescv / jupiter

f32c / f32c

larsbrinkhoff / lbForth

ucb-bar / riscv-mini