asic

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

magic asic rtl verilog vlsi foundry yosys klayout caravel netgen system-on-chip openroad openram skywater 130nm soc-design rtl2gds

Updated Sep 22, 2022
Verilog

riscvarchive / riscv-cores-list

Star

RISC-V Cores, SoC platforms and SoCs

asic fpga risc-v socs open-isa

Updated Mar 26, 2021

ultraembedded / riscv

Sponsor

Star

RISC-V CPU Core (RV32IM)

asic cpu fpga verification verilog pipeline-processor risc-v rv32i verilator riscv-linux rv32im

Updated Sep 18, 2021
Verilog

esig / dss

Star

Digital Signature Service : creation, extension and validation of advanced electronic signatures

java asic validation signature xades cades pades esignature jades

Updated Sep 22, 2022
Java

VUnit / vunit

Star

VUnit is a unit testing framework for VHDL/SystemVerilog

unit-testing asic fpga vhdl verification testbench verilog-hdl systemverilog-hdl universal-verification-methodology

Updated Sep 19, 2022
VHDL

pulp-platform / axi

Star

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

asic fpga hardware rtl ip systemverilog axi network-on-chip axi4 axi4-lite

Updated Sep 15, 2022
SystemVerilog

zssloth / Embedded-Neural-Network

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collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning

compression asic fpga deep-learning neural-network

Updated Apr 11, 2019

ultraembedded / biriscv

Sponsor

Star

32-bit Superscalar RISC-V CPU

linux asic cpu fpga verilog xilinx superscalar in-order risc-v branch-prediction coremark rv32i verilator riscv-linux rv32im artix-7 pipelined-processors

Updated Sep 18, 2021
Verilog

ultraembedded / cores

Sponsor

Star

Various HDL (Verilog) IP Cores

audio asic fpga usb rtl verilog spi sram uart verilog-hdl verilog-components verilator i2s sdram

Updated Jul 1, 2021
Verilog

VLSI-EDA / PoC

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IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

Updated Nov 29, 2020
VHDL

ucb-bar / gemmini

Star

Berkeley's Spatial Array Generator

asic accelerator dnn

Updated Sep 18, 2022
Scala

furrtek / DMG-CPU-Inside

Star

Reverse-engineered schematics for DMG-CPU-B

nintendo asic gameboy electronics reverse-engineering chip schematics game-boy silicon dmg-001

Updated Nov 30, 2020

tensil-ai / tensil

Star

Open source machine learning accelerators

machine-learning scala asic fpga artificial-intelligence hdl silicon

Updated Aug 18, 2022
Scala

secworks / aes

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Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

asic encryption fpga aes block-cipher