chisel

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Here are 106 public repositories matching this topic...

chipsalliance / chisel3

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Chisel 3: A Modern Hardware Design Language

scala chip-generator chisel rtl chisel3 firrtl verilog

Updated Jan 10, 2023
Scala

chipsalliance / rocket-chip

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Rocket Chip Generator

scala rocket-chip chip-generator chisel riscv rtl

Updated Jan 11, 2023
Scala

riscv-boom / riscv-boom

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SonicBOOM: The Berkeley Out-of-Order Machine

scala berkeley boom rocket-chip chisel riscv rtl riscv-boom

Updated Jan 5, 2023
Scala

ucb-bar / chipyard

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An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

boom rocket rocket-chip chip-generator chisel riscv rtl peripherals soc out-of-order superscalar risc-v firesim accelerators chipyard hwacha

Updated Jan 10, 2023
C

RadicalCSG / Chisel.Prototype

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Work in progress prototype for the Chisel Level Editor, for Unity

prototype unity mapping realtime chisel csg level-editor bsp leveldesign level-design constructive-solid-geometry

Updated Jun 11, 2022
C#

ucb-bar / riscv-mini

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Simple RISC-V 3-stage Pipeline in Chisel

chisel riscv rtl

Updated Jul 11, 2022
Scala

m3rcer / Chisel-Strike

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A .NET XOR encrypted cobalt strike aggressor implementation for chisel to utilize faster proxy and advanced socks5 capabilities.

socks5 chisel cobalt-strike aggressor-scripts redteaming

Updated Oct 12, 2022
C#

bu-icsg / dana

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Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

neural-network hardware rocket-chip chisel riscv rtl rocc

Updated Jan 23, 2020
Scala

im-tomu / fomu-workshop

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Support files for participating in a Fomu workshop

fpga vhdl chisel riscv verilog hdl litex migen fomu fomu-workshop

Updated Jan 9, 2023
Verilog

ucb-bar / chiseltest

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The official testing library for Chisel circuits.

testing verification chisel formal

Updated Jan 11, 2023
Scala

t3l3machus / pentest-pivoting

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A compact guide to network pivoting for penetration testings / CTF challenges.

ssh network proxy hacking socks5 chisel pentesting proxychains socks4 sshuttle burpsuite pivoting double-pivoting

Updated Sep 13, 2022

MaxXSoft / Fuxi

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Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

scala cpu fpga chisel riscv

Updated Jun 28, 2021
Verilog

maltanar / fpga-tidbits

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Chisel components for FPGA projects

fpga chisel hardware-libraries

Updated Dec 17, 2020
Scala

freechipsproject / diagrammer

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Provides dot visualizations of chisel/firrtl circuits

visualization chisel chisel3 firrtl

Updated Jan 8, 2023
Scala

chiselverify / chiselverify

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A dynamic verification library for Chisel.

testing coverage scala verification chisel constrained-random-verification functional-coverage bus-functional-model chisel-test timed-assertions

Updated Jan 5, 2023
Scala

ucb-bar / constellation

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A Chisel RTL generator for network-on-chip interconnects

hardware chisel rtl soc noc interconnect network-on-chip

Updated Jan 4, 2023
Scala

carlosedp / chiselv

Sponsor

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A RISC-V Core (RV32I) written in Chisel HDL

fpga core chisel riscv risc-v

Updated Jan 9, 2023
Scala

ovh / sv2chisel

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(System)Verilog to Chisel translator

eda transpiler chisel verilog

Updated May 20, 2022
Scala

ucsc-vama / essent

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high-performance RTL simulator

scala chisel rtl firrtl

Updated Dec 12, 2022
Scala

luoqisheng / lldb-symbolic

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lldb命令-symbolic

chisel lldb custom-commend

Updated Feb 7, 2021
Python

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