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  1. Lean but mean RISC-V system!

    SystemVerilog 137 21

  2. The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

    C++ 1.5k 415

  3. morty Public

    A SystemVerilog source file pickler.

    Rust 17 5

353 contributions in the last year

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Contribution activity

June 2022

Created a pull request in openhwgroup/core-v-mcu that received 2 comments

Fix vendor check

Fyi @MikeOpenHWGroup fixes #229. The other PRs need to be rebased of course.

+47 −0 2 comments
Reviewed 1 pull request in 1 repository
openhwgroup/cva6 1 pull request

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