kunalspathak
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661 contributions in the last year
Contribution activity
May 2023
Created 11 commits in 2 repositories
Created a pull request in dotnet/runtime that received 14 comments
Misc LSRA throughput improvements
While working on consecutive-registers, I realized few things that could help in the throughput:
1. We pass around RegisterType in various methods,…
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Opened 13 other pull requests in 1 repository
dotnet/runtime
5
open
7
merged
1
closed
- Unmark loop align regardless if we found block to align or not
-
BashToZero if both locals of
SUBare same - Fix the test build error
- Use /INCREMENTAL:NO for Debug
-
LSRA Throughput: Do not pass
RegisterTypefor non-arm - Update life of data node for simd12
- Use popcount intrinsincs in BitOperations
- Constrained mask should take into account busy registers
- Skip displaying raw instruction bytes by default for non-xarch
- Skip FP registers processing if method don't have floating points use
- Arm64: Add back the annotation in JitDisasm with the local var (+offset)
- Skip stp/ldp only for unwind portion of prolog/epilog
- [JIT]: Inline TLS field access for GC type
Reviewed 18 pull requests in 2 repositories
dotnet/runtime
15 pull requests
- Always expand cctor helpers for NAOT
- Add linux-x64 hosted tpdiff to superpmi-diffs pipeline
- [JIT]: Inline TLS field access for GC type
- Allow the user to control the MaxVectorTBitWidth and PreferredVectorBitWidth
- Expose various integer intrinsics for Avx512F, Avx512BW, and Avx512CD
- Use popcount intrinsincs in BitOperations
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[JIT] X64 - Centralize peephole optimization for removing redundant
movinstructions - Skip FP registers processing if method don't have floating points use
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Templatize
enregisterLocalVarsin various methods of LSRA - JIT: properly scrub SSA from return address buffers
- Arm64: Add back the annotation in JitDisasm with the local var (+offset)
- Skip stp/ldp only for unwind portion of prolog/epilog
- [JIT] ARM64 - Fix Assertion failed 'node->OperIs(GT_DIV, GT_UDIV, GT_MOD)' during 'Lowering nodeinfo'
- Ensure that IF_*WR_RRD formats support 4-byte SIMD instructions
- Fix processing of x86 test results
dotnet/performance
3 pull requests
Created an issue in dotnet/runtime that received 10 comments
superpmi-diff and superpmi-replay is failing with fatal error
superpmi is failing with fatal error. E.g. https://helixre107v0xdcypoyl9e7f.blob.core.windows.net/dotnet-runtime-refs-pull-85562-merge-f671ff6b18b0…
10
comments
Opened 7 other issues in 1 repository
dotnet/runtime
4
open
3
closed
- Update lvSingleDefRegCandidate after CSE to get more candidates for EHwrite thru
- Assertion failed '!"Unknown operator for loop increment"' during 'Optimize Valnum CSEs'
- Assertion failed 'node->OperIs(GT_DIV, GT_UDIV, GT_MOD)' during 'Lowering nodeinfo'
- Assertion failed '!"SSA check failures"' during 'Build SSA representation'
- Assertion failed 'isCandidateVar(fieldVarDsc) == isMultiReg' during 'Linear scan register alloc'
- Assertion failed 'refPosition->RegOptional()' during 'LSRA build intervals'
- Test failure _Avx512F_ro::JIT.HardwareIntrinsics.X86._Avx512F.Program.ConvertToVector256UInt16Vector512UInt32()