Skip to content
@openhwgroup

OpenHW Group

README.md

About OpenHW Group

OpenHW Group is a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate in the development of open-source cores, related IP, tools and software. OpenHW provides an infrastructure for hosting high quality open-source HW developments in line with industry best practices. Please see our website for membership information, latest news, and further resources.

OpenHW Group CORE-V Family of Open-Source RISC-V Cores

Below is the CORE-V Roadmap of Application class and Embedded class cores. Please see core-v-cores repo for roadmap details.

Project Repositories Table of Contents

Working Group Repo Description
Cores TG Core-v-cores roadmap
CTG meetings and minutes
CVA6 6-stage, application-class core
CVA5 5-stage, FPGA-optimized application-class core
CVW 5-stage, application-class core with education focus
CV32E40P 4-stage, embedded-class core implementing PULP extensions
CV32E40S 4-stage, embedded-class core with security focus
CV32E40X 4-stage, embedded-class core supporting X-Interface
CV32E41P 4-stage, embedded-class core prototyping Zfinx and Zce
CV32E20 2-stage, embedded-class microcontroller core and core complex
CV-HPDCACHE High performance L1 Data Cache
Verification TG VTG meetings and minutes
CORE-V Verif Common test bench for OpenHW Cores
FORCE RISC-V Advanced RISC-V instruction set generator
ARVM Advanced RISC-V Verification Methodologies
Software TG SWTG meetings and minutes
CORE-V GNU Tools GNU Tools Project for embedded-class CORE-V cores
CORE-V LLVM LLVM Tools Project for embedded-class CORE-V cores
CORE-V FreeRTOS Kernel FreeRTOS Kernel for embedded-class CORE-V cores
CORE-V FreeRTOS FreeRTOS for embedded-class CORE-V cores
CORE-V QEMU QEMU emulator for CORE-V-MCU
CORE-V SDK SDK and IDE for embedded-class CORE-V cores
Hardware TG HWTG meetings and minutes
CORE-V-MCU ASIC and FPGA MCU implementation of CV32E40P
CORE-V-MCU-DEVKIT Devkit for CORE-V-MCU
CORE-V-POLARA-APU Multicore CVA6/CVVEC ASIC with OpenPiton
Technical Working Group OpenHW project dashboard
Project Description Folders
OpenHW Project process and templates

Popular repositories

  1. cva6 Public

    The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

    SystemVerilog 1.7k 508

  2. cv32e40p Public

    CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

    SystemVerilog 703 312

  3. core-v-verif Public

    Functional verification project for the CORE-V family of RISC-V cores.

    Assembly 292 161

  4. cvfpu Public

    Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

    SystemVerilog 267 83

  5. force-riscv Public

    Instruction Set Generator initially contributed by Futurewei

    C++ 159 42

  6. programs Public

    Documentation for the OpenHW Group's set of CORE-V RISC-V cores

    JavaScript 147 79

Repositories

View all repositories