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Digital electronics, FPGAs, multi-gigabit interfaces
- Saint-Petersburg, Russia
- https://www.linkedin.com/in/pavlovconst/
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Iterative compilation and reporting scripts for AMD / Xilinx Vivado
SystemVerilog 1
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xilinx_max_power Public
Creating dummy load to dissipate maximum power in Xilinx FPGA
SystemVerilog 3
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Iterative compilation and reporting scripts for Intel / Altera Quartus
Makefile 2
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115 contributions in the last year
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Activity overview
Contributed to
pConst/basic_verilog,
pConst/vivado_design_space_explorer_template,
kaxap/arl
and 19 other
repositories
Contribution activity
March 2023
Created 1 repository
2
contributions
in private repositories
Mar 2 – Mar 6

