FelipeFFerreira / ITA-CORES
RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
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RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
The USRP™ Hardware Driver Repository
PicoRV32 - A Size-Optimized RISC-V CPU
Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.github.io/CFU-Playground/ For reference docs, see the link below.
HDL libraries and projects
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Verilog Ethernet components for FPGA implementation
An Open-source FPGA IP Generator
SERV - The SErial RISC-V CPU