olofk / serv
SERV - The SErial RISC-V CPU
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SERV - The SErial RISC-V CPU
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
The Ultra-Low Power RISC-V Core
Verilog Ethernet components for FPGA implementation
HDL libraries and projects
The USRP™ Hardware Driver Repository
PicoRV32 - A Size-Optimized RISC-V CPU
Plugins for Yosys developed as part of the F4PGA project.
The lab schedules for EECS168 at UC Riverside