SpinalHDL / VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
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A FPGA friendly 32 bit RISC-V CPU implementation
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
AMD's Machine Intelligence Library
Dozens of minimal operating systems to learn x86 system programming. Tested on Ubuntu 17.10 host in QEMU 2.10 and real hardware. Userland cheat at: https://github.com/cirosantilli/linux-kernel-module-cheat#userland-assembly ARM baremetal setup at: https://github.com/cirosantilli/linux-kernel-module-cheat#baremetal-setup 学�?x86系统编程的数十个最小操作系统。 已在QE…
Working draft of the proposed RISC-V V vector extension
Safe, fast, small crypto using Rust
A blazingly fast JSON serializing & deserializing library
A cross-platform x86 assembler with an Intel-like syntax
hipBLASLt is a library that provides general matrix-matrix operations with a flexible API and extends functionalities beyond a traditional BLAS library
Disassembly of Pokémon Crystal
Multilingual BLS12-381 signature library
mal - Make a Lisp
the official Rust and C implementations of the BLAKE3 cryptographic hash function
Basic linear algebra subroutines for embedded optimization
Disassembly of Pokémon Red/Blue
An upgrade to Pokémon Crystal. Brings features and content up to date, and adds some original content.