adam-maj / tiny-gpu
A minimal GPU design in Verilog to learn how GPUs work from the ground up
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A minimal GPU design in Verilog to learn how GPUs work from the ground up
OpenTitan: Open source silicon root of trust
Verilator open-source SystemVerilog simulator and lint system
VeeR EL2 Core
APB Logic
RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
HW Design Collateral for Caliptra RoT IP
Simple single-port AXI memory interface
RSD: RISC-V Out-of-Order Superscalar Processor
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
RISC-V Debug Support for our PULP RISC-V Cores