lowRISC / opentitan
OpenTitan: Open source silicon root of trust
See what the GitHub community is most excited about today.
OpenTitan: Open source silicon root of trust
Verilator open-source SystemVerilog simulator and lint system
HW Design Collateral for Caliptra RoT IP
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
BaseJump STL: A Standard Template Library for SystemVerilog
VeeR EL2 Core
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
A Linux-capable RISC-V multicore for and by the world
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.