lowRISC / ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
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Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
A Linux-capable RISC-V multicore for and by the world
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
Verilator open-source SystemVerilog simulator and lint system
HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
HW Design Collateral for Caliptra RoT IP
OpenTitan: Open source silicon root of trust
[UNRELEASED] FP div/sqrt unit for transprecision
A minimal GPU design in Verilog to learn how GPUs work from the ground up
RISC-V Debug Support for our PULP RISC-V Cores
Common SystemVerilog components
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
VeeR EL2 Core