HDL (Hardware Description Language) is a description language used to describe the behavior of digital circuits. Examples are Verilog, VHDL and ABEL.
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Ideas for a project combining arduino and FPGA [closed]
I would like some suggestions for my project. I need to implement ARDUINO and FPGA, nothing too complex nothing too easy. Just something Simple! where I can show that I have knowledge of these ...
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Post synthesis level simulation xilinx xst
I have written a verilog code and it is working fine at behavioral simulation level. After this I went for synthesizing the design using XST tool in Xilinx ISE 13.2. Running the post simulation level ...
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HDL Designer: What's the difference between a project and a library?
Which should I use? I'd like to use it to model circuits for homework and to possibly reuse parts circuits in other designs.
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Difference between RTL and Behavioral verilog
Can someone tell me what is the difference between RTL and behavioral Verilog code? Is there any clear cut demarcation between designs at these two levels?
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Processor - L1 Data cache interface
Sorry if the following looks like a very specialized (or programming) question, but I'm hoping there are people on this forum who have done VHDL/Verilog modeling, and might be able to answer:
I'm ...
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3answers
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VHDL Error (Simple Expression Expected)
I'm new to VHDL and I'm having a problem with my code that I can't seem to fix. We're supposed to do this using either selected signal assignment or table lookup. Mine is kind of a combination of the ...
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simulating fpga design without having the actual hardware
Im new to fpga and currently taking HDL (Verilog particularly) class. I have sufficient knowledge in digital design like combinational and sequential circuits.
I want to create a project similar to ...
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2answers
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Developing hardware in FPGA with LED Driver Chip
I asked related TI TLC5944 LED Driver questions here, here and here
Actually initially I was supposed to simulate the following design. I had to simulate the driver functionality also (as the driver ...
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In which cases should I use Z as output in HDL?
I created a simple multiplexer which feeds different input into output depending on statemachine.
Now there are states when I do not need the output so I usually set it to 0.
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What is backdoor memory access?
There is a term in HDL simulation/verification called
"backdoor memory access".
I've heard this a lot of times though I'm
not sure how is this implemented.
Also, there are a few references for this ...
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1answer
98 views
Simulating IBIS Model in modelSim
I am developing a logic in an FPGA that will act as a controller for a chip by TI. I got the TI chip IBIS model from the TI website.
My controller is ready and I want to simulate it using ModelSim. ...
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2answers
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Automating test vector in Verilog HDL
This is my first attempt at learning Verilog HDL testbench for an AND gate:
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1answer
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What is the best way to understand a large existing HDL core?
Groundhog is a open source SATA host bus adapter core written in Verilog. I was wondering if anyone had tips on how to begin to understand how it operates? Is it to go from the high-level to ...
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Developing for an FPGA using Impulse C
I am considering using Impulse C to write C code that will compile down to HDL for my FPGA. I'm curious as to what experiences people have had with Impulse C, to better understand the advantages and ...
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What is a false path timing constraint?
In FPGA world, what exactly are false path constraints for an HDL compiler? Why are they useful?
