Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips.
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25 views
ModelSim Altera: simulating the “lpm_add_sub” module?
I'm trying to simulate a verilog module that uses the "lpm_add_sub" module to provide an adder with a separate carry in (for some reason Quartus II doesn't recognise that ...
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1answer
51 views
use of library files in verilog synthesis and decompile original rtl file
I am testing a tool for verilog synthesis.I need to test that tool by using a library file or a directory but i am unable to get any example for the same.I am very new to verilog. Can any one suggest ...
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0answers
39 views
Verilog Netlist and verilog file not justifying each other
i generated a verilog netlist file with the help of a test case for 2-1 encoder .To test the netlist i draw the schematic diagram and try to find the output.I can't upload the pic of schematic which i ...
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2answers
37 views
value of variable in Veriog not defined
I am analyzing a verilog file for always.
in this, what should be the value of "en" in case first and then in second?
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1answer
45 views
Understanding Verilog Netlist
This might be a out of stand question.I am trying to understand a verilog netlist for 1 bit adder and make schematic out of it.But as i am very new to Verilog, though can understand some basic ...
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2answers
43 views
Parameterized net width in Verilog
Is something like this possible ?
parameter width;
wire[width-1] a_net = (width)'b0;
I basically need a variable to control the width of the right hand side. I ...
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2answers
50 views
Detecting 1'bx and 1'bz bits in a Verilog variable
I have a 128 bit wire:
wire [127:0] test;
I want to stop simulation if any of the bits of test is ...
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0answers
63 views
Applications with kernels that can be accelerated in hardware [closed]
Could you give me a list of applications with kernels that can be accelerated in hardware?
Some examples would include FFT, AES, Motion Estimation, Viterbi Decoder. I'm just looking for others.
To ...
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2answers
48 views
concatenate inputs in verilog
In my module I am taking two input 8-bits.
mymodule(input clk, input [7:0] AS_1,input [7:0] AS_2, output [7:0] AS)
Now I want to create a container that will ...
2
votes
4answers
138 views
Most efficient way to select between 10 large buses?
I need to select between 10 different 164-bit buses using four-bit BCD (8421, unsigned binary). What is the most efficient way to do so?
Currently I have the following SystemVerilog implementation
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0
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1answer
66 views
Accessing rows of an array using variable in Verilog
I have a module I'm writing in Verilog that effectively contains a 16 by 10 2D array. At a given point and "row", what I want is to have that data pushed to a net that can be read outside of the ...
2
votes
1answer
65 views
In verilog, what effect does the not (!) operator have on high impedance and don't care conditions?
I'm writing some verilog and simulating it using modelsim. I have a block that looks like this:
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1answer
48 views
3-phase lock loop in verilog
I want to implement a phase lock loop in verilog hdl. The input is the source voltage (which is a sine wave) and the output is theta(in terms of sin and cos).
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2answers
129 views
Square law device using FPGA
I am trying to implement Square Law Device on Virtex 5 Family FPGA but before burning it to the FPGA I was trying to simulate it in the Xilinx ISE kit. I am not sure whether the code is correct or not ...
2
votes
2answers
103 views
Verilog : Combining sequential logic with combinational logic
I am trying to implement a sequential shift and add 4bit multiplier as shown in the image.
I am having a separate module for the 4 bit ripple carry adder. I have tested the adder module and it ...
0
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1answer
63 views
2d arrays specification in verilog
I am trying to define a 2d array in verilog but I don't understand them very well in the way they are assigned. What I mean is if I define an array like
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2
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2answers
72 views
How to truncate an expression bit width in Verilog?
Consider an expression like:
assign x = func(A) ^ func(B);
where the output of the func is 32 bits wide, and x is a wire of 16 bits. I want to assign only the ...
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2answers
62 views
always statement inside case in Verilog
I am beginner in Verilog. So my question may seem easy to you, but I have difficulty in understanding structure of Verilog.
I have one module which works in two modes: read and write. In write mode, ...
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1answer
100 views
Do case statements inside a for loop work in verilog?
I am doing a code for radix-4 booth encoding for 8*8 multiplication. The logic is correct and there are no errors or warning. The output am getting is totally unrelated. i have posted the code below
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3answers
99 views
Can someone help me complete this Verilog code for this sequential circuit?
I'm still pretty new to Verilog and all and could use some help completing/fixing my code for this problem. I have made the state diagram, state table/assignment, minimized the equation, and even have ...
0
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2answers
76 views
Flip signal values in verilog simulation
I use "force" command in modelsim to force an internal signal to a specific value (not primary inputs). Sometimes, the value I force is the same as the original value.
Is there any command that can ...
1
vote
1answer
58 views
Question about forcing verilog netlist signals in simulation
I am using ModelSim to simulate a design with verilog netlist and verilog RTL.
My verilog design hierarchy is like this:
tb instantiates ...
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2answers
76 views
Creating SRAM array digitally using Verilog
As a part of my Cadence based project, I chose the topic 'Optimising power, area and timing for a 32x8 SRAM unit'. Though this is possible using NC-Verilog or by manually constructing the schematic ...
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2answers
146 views
Trouble with VGA Controller on CPLD
What I am attempting to do is create a VGA controller from a Lattice MachXO CPLD in Verilog.
The Problem
I am attempting to display the color red with a resolution of 640x480 @ 60Hz using a 25.175 ...
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1answer
53 views
Verilog: including one module in another module
I am beginner in Verilog. So I am confused in coding in Verilog. Can I use one module in another module?
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3answers
57 views
Verilog Netlist format with “\”
After synthesizing my RTL level design into verilog netlist, I find the syntax confusing. Here is what I mean.
RTL compiler gives me:
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1answer
64 views
VerilogIn and Spice out in Cadence or Synopsys
I want to convert a verilog netlist into a simulatable SPICE (or HSPICE) format. I have seen people talking about verilog-In and spice out in Cadence. How does this process actually work? What are the ...
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2answers
84 views
Post synthesis level simulation xilinx xst
I have written a verilog code and it is working fine at behavioral simulation level. After this I went for synthesizing the design using XST tool in Xilinx ISE 13.2. Running the post simulation level ...
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2answers
141 views
Difference between RTL and Behavioral verilog
Can someone tell me what is the difference between RTL and behavioral Verilog code? Is there any clear cut demarcation between designs at these two levels?
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1answer
103 views
Difference between @* and @(*) in verilog
What is the difference between always @* and always @(*) in verilog?
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1answer
118 views
How to find the critical path delay of a big combinational block
I have a 54*54 multiplier, i want to find the critical path delay.how do i go about, should i clock the module in order to find the delay?
2
votes
1answer
109 views
What does non-combinational area represent in synopsys design compiler
I have designed a ripple adder using full adders. In order to find delay incurred to perform this addition I included a clock in each full adder module. In my main code I instantiated these modules to ...
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votes
2answers
251 views
Altera DE1 seven segment display
What I am trying to do is, I want to use Key 0 as a upcounter and key 1 as a downcounter in the same program. I can do that separately. So, when enable is triggered, pressing key 0 will increase the ...
0
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1answer
123 views
Problem initializing Xilinx BRAM
A while ago I added a feature to GNU binutils to convert files to verilog mem files, suitable for reading with $readmemh. The output is very close to what you might get with xilinx's data2mem ...
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2answers
99 views
when do we use disable statement in verilog? is it possible to disable a block outside that block?
I want to disable a block by using an if condition outside that block. I am getting error:
UNEXPECTED DISABLE EXPECTING ASSERT
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2answers
90 views
Nonblocking simultaneous assignments to wires and registers in Verilog
I am interested to write Verilog module which simultaneously will update several outputs Something like following code, makes 3 operations at the same time (clk 10):
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2answers
77 views
Execute module one after another using flag status
I want to execute 2 modules, one after another using one flag signal
What changes do I have to do in code below to the modules. I have used delay_4 and multiply.
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1answer
134 views
Verilog output port is high impedance (Z) when driven by a sub module
I'm writing code for shifting 4-bit using carry flag for generating delay using instantiating but when I'm instantiating in top module output of top module temp1 ...
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1answer
122 views
I am not able to instantiate sub modules inside always block
I am designing a floating point unit in verilog. I have designed separate adder, shifter and multiplier modules in verilog. I want to call all these modules and make a single main module. I am not ...
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2answers
190 views
How to give a 2-D array as output of a function in Verilog?
I have to write a code to generate partial products for a 53*53 radix four booth multiplication. I declared a function as shown below; it is showing the error message ...
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3answers
159 views
Open Source verilog synthesizer
I'm looking for an open source verilog synthesizer. I am using Icarus Verilog as a verilog simulator. Originally I was going to use it for both simulation and synthesis, but found out the tool no ...
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votes
1answer
86 views
Inputs are are not able to force to DUT in Testbench
I have written tb in verilog. My testbench inputs are going at high impedance i.e. zz. My dut is not able to force stimulus.Please help me as I m not able detect the problem in my testbench.
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2answers
274 views
How to Add the Xilinx Library to Modelsim
I'm trying to simulate an example design of an IP Core, but the version of ModelSim I have installed (Altera Edition/Linux) does not link to the Xilinx library. How can I permanently or temporarily ...
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1answer
68 views
Test_bench in Verilog using Task
I have written testbench in verilog. All the test cases define in task works independently well but when I try to run both task then it give proper output for 1st task in task_operation but not for ...
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1answer
82 views
How can I detect a pulse from a device with the AC'97 component of a Xilinx Atlys board?
I have a digital device which transmits rapid pulses over a 3.5mm audio cable, indicating that some event has occurred. I want to connect that device to my 3.5mm line in jack on my Atlys board and ...
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votes
2answers
93 views
What do square brackets represent in verilog?
Can anybody help? I know it must be very simple but I am still confused with the following:
M41_1(input0[1],input1[1],input2[1],input3[1],sel0,sel1,out[1]);
What do the numbers in the square ...
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votes
2answers
334 views
MUX verilog code
Can anyone explain the difference between the two codes below. Both written in Verilog, Xilinx. If someone can explain how the second one works would much appreciate it.
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3answers
88 views
What is the mechanism behind RO or WO and WR registers?
In embedded systems you have read only and write only registers. How are the two type distinguished in the netlist? I can not understand how one build a flop which you can only write and not read ...
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1answer
151 views
Verilog interfacing with C#
Right now, I am taking a course on Verilog HDL, however, our instructor gave us a machine problem wherein we are required to implement a program using verilog while having C# as our main gui. The ...
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4answers
277 views
How to think while working with VHDL or Verilog
All of my experience belong to general purpose programming languages e.g; c/c++ etc where each instructions are executed one after the other but it seems in VHDL/Verilog, all the instructions are ...
