Consider instead more specific tags, e.g., dram, sram, flash
2
votes
1answer
30 views
Writing data on EEPROM or Flash memory of the PIC18F47J53
So I am using the 18F47J53 in Hitech PICC18-PRO compiler with MPLAB-X IDE, and for some reason there happens to be absolutely no support for the reading/writing function to either the flash or the ...
1
vote
1answer
25 views
Memory logic array blocks VS M20K
I am looking at the Stratix V overview Table 1. In it, they distinguish two types of memories:
M20K memory blocks
Memory logic array blocks
What are the ...
0
votes
1answer
66 views
BRAM memory FPGA
Can someone explain how does a BlockRam in FPGA work.
I was creating a memory for 128k and could not figure out how would I create a memory module for it.
3
votes
1answer
95 views
How to add memory to an ARM Cortex Microcontroller
I am looking into a design that would use the ARM Cortex M4F core but am just the software engineer for the project. The EE tells me that there will be an 64 MByte sdram memory module connected to the ...
0
votes
1answer
48 views
Building memory system adresses with decoders
Well I got the following (multiple choice) question. Even with the result given I have 0 idea how they could come to the conclusion..
With 64 memory elements of size 1Mx4 and several 2-input ...
0
votes
1answer
48 views
Address decoding from memory map
I am struggling to find the bits which dont matter when I have a memory mapped system with several devices connected.
The memory map is given by
I need to figure out which bits I should pass to ...
2
votes
1answer
97 views
What is DDR software leveling?
What is DDR software leveling ?
How it is different from DDR2 and DDR3 ?
Why it is required and important ?
Is there a hardware leveling ?
I have found some explanation here about DDR3 and a ...
0
votes
3answers
26 views
K9F1208R0C-JIBO data extraction
I have a old PDA board, it is not working, but I want to see the content of memory chip for this board, as far as I know there [might be] some interesting software on it, but the PCB is dead, so I ...
0
votes
0answers
48 views
Doubts in two level cache system
A computer system has an L1 cache, an L2 cache, and a main memory unity connected as shown below. The block size in L1 cache is 4 words. The block size in L2 cache is 16 words. The memory access times ...
-3
votes
0answers
40 views
In memory pipelining, how is this statement true?
In an instruction execution pipeline, the earliest that the data TLB (Translation
Lookaside Buffer) can be accessed during effective address calculation has started.
0
votes
1answer
46 views
Terms (bank,latency) in main memory?
A CPU has a cache with block size 64 bytes. The main memory has k banks, each bank being c bytes wide. Consecutive c - byte chunks are mapped on consecutive banks with wrap-around. All the k banks ...
2
votes
5answers
117 views
How does register type modifier work on different CPU architectures?
This question is to clarify my doubt against this register storage class.
when a variable is register qualified ,compiler puts the variable in a cpu register other than RAM for ease of access. so ...
0
votes
0answers
32 views
Memory technology survey?
I did a comparison on what I could find about access times for different memory systems, could you please say if these numbers are approimately correct (I use an Altera DE2 FPGA)?
SDRAM: Slower that ...
-2
votes
1answer
105 views
How to make MCU with 256kB memory?
(Reposting)
I have 48MHz clocked ADC that outputs data continuously. My MCU will take the data at some interrupts and need to send it to iPhone. The amount of data collected are abt 178k Bytes. I ...
0
votes
1answer
112 views
What's the usage of the three boot mode of STM32f103?
If you see in refrence manual of STM32f103, you can see three boot mode for it. well, What's the usage of the three boot mode?
please say to me by example for each mode.
1
vote
2answers
107 views
How do you read from Static Random-Access Memory (SRAM)?
I have searched online, but I do not understand very well the procedure for reading from SRAM?
I have an exam about digital electronics and two of the questions may be what is an SRAM and how the ...
0
votes
2answers
54 views
What is the main Computer Memory Addressing Mechanism for Semi-Conductor Memory? [duplicate]
Most semiconductor memory is organized into memory cells or bistable flip-flops, each storing one bit (0 or 1).
How exactly are the needed '1's or '0's taken from Memory? What mechanism or algorithm?
...
0
votes
3answers
68 views
How is 'specific' data found and taken from a Semiconductor Memory Source?
In a semiconductor memory chip, each bit of binary data is stored in a tiny circuit called a memory cell consisting of one to several transistors. Volatile type.
Suppose an application stored its ...
2
votes
2answers
125 views
Using multiple DDR3 controllers on FPGA
We are designing an image processing pipeline on an FPGA which will need the use of memory interfaces at various pipeline stages. Because of the size of the memory required we decided to go with a ...
1
vote
1answer
105 views
How to select correct SPI flash for specific micro-controller (pic32mx795f)?
i'm interesting on how to correctly select SPI flash for microcontroller.
specs:
High-Performance 32-bit RISC CPU:
MIPS32® M4K® 32-bit core with 5-stage pipeline
• 80 MHz maximum frequency
• 1.56 ...
4
votes
6answers
296 views
Exploiting stack buffer overflows on an Arduino
Is it possible exploit stack buffer overflows on an Arduino board?
2
votes
1answer
80 views
Can't write more than one byte to the SST39SF010A Flash!
I use code composer to program the TMS320C31 DSP (through MPSD) to write to the SST39SF010A flash. I can successfully write one byte to any location of the flash by following the "Chip Erase" then ...
0
votes
1answer
64 views
Ratio between register and primary memory access?
I've been doing research to find how much faster register access is compared to primary memory. I find the ration is about 100 times faster, can that be correct, has it always been about that number ...
4
votes
2answers
319 views
Building small, low-power pedometer/odometer with memory and time/date log
Background
I'm a researcher looking at the use of personal tracking devices and apps (like Strava app or Fitbit device) for cycling. At the moment I'm designing a simple experiment where I want to ...
1
vote
1answer
84 views
Memory modelling and Memory module in Verilog synthesis
I am using a synthesis tool and when I am synthesizing a verilog file
module test();
reg reg1;
reg [1:0] reg2;
reg reg3 [1:0];
reg [1:0] reg4 [0:4];
endmodule
...
2
votes
2answers
325 views
the . hex file we burn goes to flash memory or RAM or EEPROM of Atmega8?
The flash memory of atmega8 is 8Kb.
Is this the maximum size for the .hex file, or it the max memory which i can allocate to variables in my code?
If none of the above is true, than what is memory ...
1
vote
2answers
265 views
Differences, uses, and theory of volatile and nonvolatile memory?
I understand the basics of volatile and nonvolatile memory. Volatile memory requires a constant power supply to retain data whereas non-volatile memory does not require a constant power supply to ...
2
votes
1answer
80 views
What “external” source can change a General Purpose Working Register if no interrupts are enabled?
I have a 8-bit ATmega processor (from the 48/88/168 family) and encounter a strange behavior: after a brown-out reset, sometimes (around 20%-30%) it fails to start after a short brown-out. It always ...
0
votes
2answers
99 views
PC shares memory with external microcontroller
I'm looking for a PC hardware interface that matches these needs-
The PC will constantly be busy performing calculations. Each time there is a calculation result (every ~1ms) I want it to share it ...
0
votes
0answers
39 views
Will this RAM bypass interfere with linux's total memory count? [duplicate]
As the patent in this question shows, it may be possible to hijack a computer by bypassing the memory controller.
If it's true that it only hijacks part of the RAM at a time, does that mean that it ...
0
votes
2answers
96 views
Can this RAM bypass be prevented by making the particular memory controller “not idle”?
AbsoluteƵERØ showed me that memory can be bypassed at the memory controller. Can linux (be made to) detect foreign connections to the ram bus?
by showing me this patent: ...
0
votes
0answers
123 views
Problem running C++ function from STM32's SRAM in Keil microVision
I'm using Keil uVision 4.6 to write a C++ program for SMT32F103RE.
I need to run one of my program functions directly from SRAM, so I devided my SRAM into two separate regions:
...
1
vote
1answer
122 views
PIC16: Out of Data Space - Make use all available banks
I'm using a Microchip PIC16F1825 with the XC8 (v1.12) compiler and defining some arrays (size between 16 and 64 bytes). I was able to declare them (linker output below). However, as soon as I try to ...
42
votes
9answers
4k views
How can anyone use a microcontroller which has only 384 bytes of program memory?
For instance a PIC10F200T
Virtually any code you write will be larger than that, unless it is a single purpose chip. Is there any way to load more program memory from external storage or something? ...
1
vote
3answers
139 views
Are most RAM/Memory cells done with Inverters?
As far as memory cells go (SRAM/ROM/Registers) in simple chips everything i've looked at seems to use the Two-Inverter CMOS schematic (Just from readings/googling and such).
In I guess "real life" ...
4
votes
1answer
62 views
How to best understand cache associativity?
AFAIK this definition is the most clear and physical:
Associativity number = Number of comparators.
Is it correct? Could you make a more precise / better definition?
The wikipedia illustration is ...
0
votes
2answers
247 views
8085 Memory address decoding with a NAND Gate
I have a problem for homework that has me stumped. Basically, what I'm given is 2 R/WMs, each 2048 bytes * 4. Connected to each of their CS pin is a NAND gate with pins A12-A15 connected from the 8085 ...
5
votes
3answers
592 views
What are the implications of using PROGMEM?
With large amounts of text variables, I've found it necessary to store them in the Flash memory using PROGMEM. What are the positive and negative consequences of storing large variables in Flash ...
1
vote
1answer
109 views
Interfacing SJA1000 to Spartan6 FPGA
As the title says, I would like to interface an SJA1000 CAN controller to a Xilinx Spartan6 FPGA.
The SJA1000 has a shared 8-bit address&data bus with an address latch signal and either separate ...
0
votes
0answers
58 views
Writting in a USB memory
I have a AT91SAM7X-EK card from atmel, and I'm trying to write a string into it's memory then I want to read it back.
I order to do that I parsed the available devices using
...
5
votes
9answers
708 views
Microprocessors/Microcontrollers - Do registers have addresses?
My Embedded Systems professor keeps referring to the memory locations of registers as their respective "addresses". I'm confused by this; I was always under the impression that in any microprocessor, ...
0
votes
1answer
213 views
GDDR5 overclocking [closed]
Why does a GDDR5 memory which is designed to work at 1250MHz gets slow at 1450MHz? Because of ECC check start? Because it is not supposed to work at that frequency(hard-coded?)? Because of some ...
2
votes
3answers
391 views
Interfacing with RAM from a PC, e.g. SDRAM / DDR, to a microcontroller
I'm looking into interfacing standard PC form-factor SDRAM or DDR sticks to a microcontroller, but I can't find any definitive details on how they work in terms of how the bus works. I guess it's ...
1
vote
1answer
109 views
How to erase stored data in MRAM memory devices
When searching in Google about MRAM I was only able to find the reading and writing process for MRAM. How does erasing happen in MRAM? Also why there is no need of error correction and checking ...
4
votes
2answers
318 views
How NAND Flash controllers erase single pages efficiently?
I'm working on some code to manage a NAND flash and I need to erase single pages, given that the smallest erasable unit is a block, the only solution I could think of is to:
Erase a reserved block
...
1
vote
2answers
225 views
ARM (Cortex-A8) High Speed Bus?
I need to communicate from FPGA to ARM with about 16GBits/s...
Is there a Bus which I can use? Or how to solve this problem?
The FPGA receives data over LVDS. This data schould be post-processed in ...
1
vote
0answers
67 views
Interfacing NAND flash with USBMSD
I'm trying to read files from a NAND flash (K9LAG08U0M) that I took off an old MP3 player, so far I've been able to read the NAND contents successfully by interfacing it to my PC as a USBMSD (Mass ...
2
votes
1answer
654 views
How to access RAM for use with an FPGA for high performance computing
I am exploring the idea of using an FPGA for linear algebra. I would like the ability to work on large matrices (> 4 GB). But modern high-end FPGAs have RAM on the order of megabytes.
Please describe ...
3
votes
3answers
278 views
Sequential Logic - Primarily For Signal Storage?
New here :D
I've been reading David M. & Sarah Harris's book "Digital Design and Computer Architecture" and came to wonder about the role of sequential logic. To me, it seems that the ...
0
votes
1answer
153 views
Ardupilot, atmega1280 and barometer
I'm working on a project and I need to know where the information taken by the barometer sensor are stored.
I think in the eeprom, but exactly where? Is there a specific address or register memory?
...
