The ddr tag has no wiki summary.
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1answer
91 views
What is DDR software leveling?
What is DDR software leveling ?
How it is different from DDR2 and DDR3 ?
Why it is required and important ?
Is there a hardware leveling ?
I have found some explanation here about DDR3 and a ...
4
votes
2answers
63 views
Debugging DDR bus issues
We have an SBC board, in the style of the Leopardboard or Beagleboard, that is misbehaving. It's based on the Leopardboard design (TI-DM368 CPU, DDR2 RAM, NAND Flash).
Developing software on the ...
1
vote
1answer
36 views
DDR2 CAS Latency - is it fixed to clock-cycles or time?
We have a (new, prototype) board that is, at best, temperamental. It's using a Micron MT47H64M16HR-25:H DDR RAM, the design reference board uses a Micron MT47H64M16HR-25E:H. Only one letter different, ...
8
votes
1answer
312 views
Is there a PCB-layout related reasoning behind DDR memory package and footprint?
BGA DDR packages have a unique footprint. There are two columns of pads on both sides of the device, and an empty column in between.
Is there a reasoning behind the placement of these pads (in ...
2
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3answers
367 views
Interfacing with RAM from a PC, e.g. SDRAM / DDR, to a microcontroller
I'm looking into interfacing standard PC form-factor SDRAM or DDR sticks to a microcontroller, but I can't find any definitive details on how they work in terms of how the bus works. I guess it's ...
1
vote
1answer
188 views
Memory IC width vs depth
Given a need for a single 2G × 32 bit DDR3 memory block, which configuration would be ideal and why?
A: Two 2G × 16 bit memory ICs
or
B: Two 1G × 32 bit memory ICs
I think that A ...
3
votes
1answer
735 views
Speed difference between SRAM (Static RAM) and DDR3 RAM
This is more of a computing question, but only electronics geeks would know such things. Today's computers use multiple layers of memory in order to work with data quickly. Currently CPU speeds are ...
6
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3answers
779 views
Question about trace length matching patterns for high speed signals
A colleague and I had a discussion and a disagreement about the different ways high speed signals can be length-matched. We were going with an example of a DDR3 layout.
All the signals in the ...
0
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1answer
92 views
Can I use LPDDR with Cyclone III FPGA?
I have seen the Cyclone III datasheet and it claims DDR and DDR2 compatible PHY.
But was looking some good LPDDR chips for my design.
Could I use the PHY inside of Cyclone III with LPDDR ic?
Do you ...
2
votes
1answer
78 views
power down some but not all DDR on a bus? And I'm thinking of DDR3/3L and DDR2.
I'm starting to learn about power managment, and am wondering, can you power off a DDR module on a memory bus while others are still in use? Or does that mangle signal integrity on the bus? I assume ...
6
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3answers
707 views
DDR1 Layout Considerations - DOs and DONTs
I am novice to high speed design.
Before getting in to DDR, I recently learned about impedance matching and how it is done, likewise I learned about length matching and how it is done.(Baby steps ...
