In the semiconductor and electronic design industry, SystemVerilog is a combined hardware description language and hardware verification language based on extensions to Verilog.
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How to use a module in verilog as in build operator like OR, AND, XOR etc. function?
I wanted to module GR as the operator. how can I?
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1answer
30 views
“Numeric value exceeds 32-bit capacity” error in QuestaSim
In the testbench for a SystemVerilog module, I have the following array declaration and initialization:
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1answer
41 views
How can assign a synthesizable string to a byte array in SystemVerilog?
I want to initialize a byte array (or any other possible type) to a long string. For example define: string str = "abcdefg". I read these two links (1 & 2) but ...
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2answers
61 views
Assigning x in verilog
Assume there exists a 1 bit data output port and a 1 bit dataValid output port for a module. Is it OK to assign 1'dx to the data output when dataValid is assigned 0? Will this create synthesis issues?
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32 views
Would you let me know how to use the DPI and DPI-C?
Hi when I use the systemverilog, there are some confused point.
first one is distinguish about DPI and DPI-C.
as following example used DPI not DPI-C . but As I know DPI-C is used to in C.
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1answer
36 views
Task doesn't work in verilog
I created a module that first sorts a byte array then choose last element as minimum.(just for practice). When I moved sort to the task block, it doesn't worked as well as before. How can use task ...
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5answers
148 views
Blocking vs Non Blocking Assignments
I have been having a really hard time understanding the difference between blocking and non-blocking assignments in Verilog. I mean, I understand the conceptual difference between the two, but I am ...
3
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1answer
46 views
Modelsim - Weird verification problem with DDR and Xilinx UNISIM
I am doing verification of VHDL component using OVM and ran into serious problems. I have found that problem is in one specific component and created environment specifically for it. It's a RGMII to ...
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31 views
Register for Headers in HDL
I have a protocol that has a header, to simplify code writing, I created a struct with the different header fields.
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2answers
81 views
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72 views
How to use UART port for sending status in verilog
I am developing various verilog modules with state machine for a fpga board.
When i have done simulation of the modules i have used "$display" to get what is happening in the module or otherwise the ...
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2answers
138 views
32 Bit Increment Circuit and Verilog Program
I have to build a circuit that stores a 32-bit number. The circuit features a control signal inc that, when active, increments the stored value by 3 in each cycle. If inc is 0, the circuit simply ...
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67 views
T Flip Flop Verilog
I don't quite understand flip flops that well so I just wanted to see if this verilog code I wrote makes sense and if the outputs are what are expected from a T Flip Flop
verilog code:
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1answer
73 views
Verilog 8 Bit ALU
Here's what I have so far but I'm stuck with what to do for the f values for the last two and whether the if statement syntax is correct. Any tips?
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1answer
77 views
Verilog BitSet Circuit
A specific type of bit-level manipulation consists in setting or clearing one single bit in a multi-bit value, given its index and its new value. This operation can be implemented in hardware by a ...
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1answer
146 views
Eight bit ALU with Overflow in Verilog [closed]
I have the above assignment and here's what I have so far in verilog:
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1answer
54 views
Demux realisation in hardware
Following the previous post
Output of XOR gate with high-impedance input
I am interested further how four-valued logic of SystemVerilog gets eventually implemented in hardware.
Could someone correct ...
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1answer
48 views
Interface array forwarding and modports
QUESTION
Are interface parameters for a module automatically deducted from the interface instance that is connected to the module instance?
Background
I am designing a System that provides a ...
3
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2answers
137 views
System Verilog generic modules and unused ports
I have written a parametrized FIFO for reuse. Since I want to use the FIFO in multiple places I added several output signals for the fill state, like full, ...
2
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0answers
146 views
How to create .vcd file for power analysis through xpower(xilinx 10.1) software?
I had a verilog code. I did xpower analysis without .vcd file, with .vcd file(using simulate post route & route model) and .vcd file (using ...
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1answer
117 views
Declare queue in verilog
I wrote a simple code to declare a queue and use it in verilog, but it always gives an error when I use ISE 14.6 synthesize tool.
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414 views
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68 views
SystemVerilog interface blocks and Altera Quartus Design Partitions
It appears that Quartus (including the latest v15.0) does not look at modports when determining the direction of the ports in SystemVerilog interface blocks.
The fitter complaints that the design ...
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1answer
79 views
Unable to understand Verilog syntax
I found an example Verilog code as following:
module test #(parameter p=1) ();
localparam [1:0] lp = ~(p)'(1'b0);
endmodule
I'm unable to undestand the ...
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338 views
How to check past values in system verilog assertions?
I want to check if a signal was asserted in past 8 cycles.
I can do it using $past in system verilog :
$past(signal,1) or $past(signal,2) or $past(signal,3) or $past(signal,4) or ....... ...
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1answer
76 views
Addition in verilog: simulation doesn't match synthesis
I come from very predominant background in VHDL and have recently been doing a lot more coding in SystemVerilog. I've noticed a couple of strange behaviours that I don't entirely understand.
Summary
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why use sum of product and not product of sum in programmable logic array and programmable array logic [duplicate]
I am confused why only SOP(sum of product) are used in PLA and PAL and not POS(product of sum)
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344 views
systemverilog structure initialization with default = '1
Can someone shed light on what this SystemVerilog code should do:
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1answer
34 views
How can module TB trap $fatal from module A
I have an RTL simulation where module TB is the testbench for module A.
Module A generates $fatal when it meets some condition it doesnt like.
Module TB generates/collects transactions to/from A. Is ...
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1answer
72 views
What are the Synthesis Tools supporting SystemVerilog 2012?
I am trying to compile and synthesis a design wrote with sv2012 , I was able to use vivado2014.1 to compile fine but i got a problem in synthesis since as per Xilinx Vivado doesn't support ...
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2answers
659 views
what is difference between pass by ref and pass by val in systemverilog?
I just want to know what is difference between pass by ref and pass by val in systemverilog?
I can't find any example.also expecially, what is this? Does anyone know what is this and explain?
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1answer
362 views
Is event control iff in systemverilog the same like clock gating?
I have found like this code.
Always @(posedge clk iff rst==0 or posedge rst)
I think above code like clock gating code.
As I know , when rst is 1 then this block ...
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1answer
378 views
How to access generated instances systemverilog and Vivado 2014.1?
I generate instanced using the following code:
I try to access them like that:
R[0].router3d.address= 0 ; // for example
The simulation went fine But the code is not synthesizable with the ...
1
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1answer
382 views
System-verilog generate statement
I wrote a module in System Verilog, i need 32 modules, so i am using generate statement for instantiation.
The problem is that in every posedge of clock i need to instantiate new values to the ...
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2answers
330 views
How to remove this warning in Verilog?
I took a signal sum[8:0] in my code. Further, I need only sum[8] in my code (M.S.B of sum). So I used the statement ...
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1answer
58 views
System verilog: define empty vector
In VHDL I can write (0 downto 1) and will generate a Vector with 0 elements.
I want to do this to "rightalign" a field in a union, if needed.
Samplecode:
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3answers
268 views
Do $fopen and $fwrite works with FPGA implementation also?
I used $fopen , $fclose and $ fwrite in my verilog code. It worked with simulation but when i did FPGA implementation it is not working. My question is that these works with FPGA implementation also ...
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51 views
What do the following terms mean for verification engineers?
When it comes to verification of digital circuits, what is the difference between the meaning of the following terms:
What is the difference between specification and requirement?
What is the ...
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1answer
719 views
Running UVM example on MODELSIM - ALTERA 10.1d
I want to compile and simulate this simple UVM example using Modelsim-Altera 10.1d tool.
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1answer
156 views
Non overlapped implication(|=>) used in system verilog assertion
I know that if I use
s1 |=> s2
the consequent sequence expression s2 will be evaluated on the next clock tick. However, if there is no clock(combinational ...
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1answer
105 views
System Verilog Adapter Interface
I am using Xilinx's PCIe Core, which in its latest version duplicates the AXI valid signal 22 times.
This means writing something like {22{1'b1}} every time I try ...
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2answers
173 views
What do the terms code coverage and functional coverage refer to when it comes to digital design verification
It seems that verifying a design is a more complex task than the actual design itself and takes a lot longer to carry out. We may even need to create testbench to very the original testbench that ...
2
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2answers
76 views
Modelling current to remain in particular range for fixed simulation time
I am a novice in SystemVerilog. I wish to know how to model a 8-bit signal X to attain four levels for certain ranges of time. For example,let the legal values of X be from 40 to 80(40 < X < 80)
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38 views
Why the port type of this module default to 'var'?
In "IEEE Std 1800-2012 SystemVerilog", p. 668, I find this:
module mh11(output integer x); // output var integer x
I wonder why it is default to 'var' but not ...
3
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2answers
305 views
Generate flip-flops using only combinational logic
Just for fun, I wanted to design and simulate D-type flip-flops using only combinational logic in Verilog (or SystemVerilog). I am using using Verilator for the simulation.
My initial attempt, which ...
0
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1answer
325 views
Creating SystemVerilog module using for loop and separate custom module
I am trying to create an n-bit barrel shifter using the diagram in the answer to this question: http://stackoverflow.com/questions/26551049/vhdl-n-bit-barrel-shifter
I've read that if the variable in ...
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1answer
398 views
Spawning threads in SystemVerilog with input variables
I run onto a rather confusing situation where I was writing a code for a UVM monitor. This module performs these operations in order:
Listen to channel (virtual interface) until intercepting one or ...
2
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1answer
146 views
Functional and Timing accuracy of an RTL Model
I am sometimes really confused by the abusive use of jargon in EDA/VLSI design articles and books. With no precise definitions, its upto the reader to make interpretation which is very ambiguous and ...
0
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1answer
94 views
Inheritance of properties
Is it possible to inherit some properties from the scope that we invoke a function? A code snippet might help more to explain:
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4
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2answers
112 views
Secure signals on boot time to prevent unwanted operations
How can I be sure that at boot time my module won't get random values to it's control signals and write to an address* before I reset the module?
*(or anything that shouldn't be done before reset)
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