A CPU, or Central Processing Unit, is the heart of any digital computer.
0
votes
1answer
41 views
Interface 10 image sensors to Linux CPU
I need to process image data from 10 image sensors simultaneously (namely from OnSemi MT9V022s or similar). All 10 sensors will be externally triggered by a common signal. Ideal solution would be to ...
-3
votes
0answers
55 views
circuit diagram for TI processor [closed]
I have a project in a total of 9 schematic pages and wanted some expert to review the schematics and comment in case if there is error in the circuit
Regards
Nick
0
votes
0answers
18 views
How are lanes managed on PCIe 3.0 controller embedded on recent Xeon processors?
I'm using several PCIe 3.0 extension cards (GPUs and Infiniband interconnects). I'm wondering how lanes are actually managed and if I may optimize my devices by changing ports or by using some ...
1
vote
3answers
130 views
Is it possible to replicate the ENIAC using logic gates
Can one rebuild a small scaled model of the original ENIAC computer using only logic gates?
1
vote
3answers
133 views
Can you make a CPU out of logic gates
If i solder together enough binary adders, binary subtractors is it possible for it to work like a modern (very very slow) CPU (Such as one found in a graphics calculator).
-3
votes
1answer
89 views
What are common EE computer tasks? [closed]
I am an electrical engineering student looking to build a desktop computer. That being said, I would like to configure it to run common EE tasks as efficiently as possible. Therefore, I am trying to ...
6
votes
2answers
158 views
How electronic components like diodes, capacitors, resistors are added to CPU?
I have been trying to understand how CPUs are manufactured with those large and complex circuits. But Making of CPU only talks about projecting transistor diagrams(May be that is the major part). Bu ...
19
votes
7answers
5k views
Is transistor the only electronic component on a CPU?
I have been reading about CPUs recently and came to know that all logical blocks and memory on CPU can be made out of transistors. So is it the only electronic component on CPU?
Edit(Made after first ...
4
votes
4answers
922 views
What is the densest part of an integrated circuit?
Also, which part of an integrated circuit has been affected by Moore's law most?
Is it the memory (caches, embedded memory, etc.)?
Or is it the logic (execution units, control units, etc.)?
Or ...
-1
votes
1answer
39 views
How is data transmitted on different media? [closed]
Thinking about computers primarily, I'm trying to get my head around how data is transmitted along various transmission media. In particular, I'm getting confused between the use of electromagnetic ...
2
votes
1answer
51 views
How instruction skipping is avoided during procedure calls in pipelined architectures?
I have a question regarding a PC register (IP in x86 lingo). In most architectures it is updated during an execution stage and thus stores an address of a next instruction to be fetched. It seemed ...
0
votes
0answers
54 views
Finding the effective switched capacitance in Intel processors
I need to able to calculate the power consumption of an Intel processor using the equation,
P = C * (V^2)*f
where C, V and f are the effective switched ...
0
votes
1answer
40 views
How to calculate how much data a Core 2 duo E8 can write to the RAM per second?
I'd like to know how exactly I could calculate how much data the Core 2 duo E8 can write to the RAM per second, given that it is not overclocked and the RAM is 333MHz-DDR3?
13
votes
5answers
2k views
Does a CPU completely freeze when using a DMA?
I have pretty straightforward question, but I couldn't find an answer to it anywhere.
On a Von-Neumann system where code and data live in the same RAM, the CPU must fetch all its instructions from ...
1
vote
1answer
46 views
Microinstructions: Why is H = H – MDR illegal if H and MDR use two different buses?
The book here (on page 14) states this:
Similarly, H = H –
MDR is illegal too, because the only possible source of a
subtrahend (the value being subtracted) is the H register.
From my ...
-3
votes
1answer
59 views
1 bit shannon entropy CPU instructions? [closed]
It has been proved, that the xor operator is suitable for entropy accumulation, due to its theoretical shannon entropy of 1 bit.
There are six truth tables with ...
1
vote
1answer
90 views
GFlops for IBM Power8 processor
What is the number of GFlops per cpu cycle for IBM Power8?
Flops per cpu cycle is obtained as ( number of double precision floating point numbers fitting into one vector processing unit (if any) ) * ...
9
votes
6answers
726 views
memory for the simplest possible computer (Pi0K)
I'd like to build the simplest possible computer. I don't care about speed or storage, indeed having slow speed and low storage is a huge advantage as I want to build it out of transistors (ideally ...
3
votes
4answers
553 views
Real time operating systems
I have been asked this question: “Do you think the system will need deterministic time or real time responses?” The problem I have is distinguishing the difference between the two. I know that a real ...
0
votes
2answers
49 views
What happens if a branch prediction overwrites a value?
We are just learning about branch prediction so I might not totally understand how they work, but as I understand it, the branches are set to predict either taken or not taken. The pipeline will start ...
0
votes
1answer
94 views
Can an FPGA connected to a CPU via PCIE access peripheral devices?
Is it possible for an FPGA connected via PCIE to a CPU, to directly access peripherals (USB Ports, data, Ethernet, etc) connected to the same CPU via a chipset? I had an Intel based system in mind, ...
0
votes
1answer
43 views
Choosing components to clone ZX80
I have an idee fixe to make a clone of Sinclair's ZX80 computer.
So now I'm trying to find out which ICs I need for the basic prototype - and here are a few questions:
it seems ...
0
votes
3answers
70 views
Programmed IO vs interrupt for devices
Although I can understand the difference between programmed IO (PIO) and interrupt (INT) transfers, still there is something vague.
In PIO, the processor repeatedly checks READY pin to see if the ...
1
vote
1answer
54 views
Performance comparison of dual core and quad core processors with same TDP
Athlon X2 340 (dual core) and Athlon X4 740 (quad core) from AMD have same architecture and both have same TDP (65W). They also have roughly similar frequency. Does this means that at full load, the ...
-2
votes
1answer
83 views
Where is the control, address and data bus in a computer
So have been reading up on data buses, address buses and control buses and I understand what they do, but am confused about where they can physically be found. Some books/sites I have found state that ...
1
vote
0answers
40 views
State Machine for I-type MIPS instructions
I need to design a multi-cycle CPU in Verilog for MIPS instructions, but I'm still trying to fully understand the datapath and control. I found a state machine design for a MIPS instruction ...
0
votes
1answer
65 views
ESD protection for work with CPU/GPU
I am ready to perform a BGA reballing operation on my ps3's CPU and GPU chips. Should i take into consideration electrostatic discharge or is it not needed?
How can i protect from these dangers? Are ...
1
vote
1answer
532 views
Is there a way to build a 2k*12 RAM using only 2 4k*4 Chips
Okay so I know when I need to build a parallel design I can put them near each other and make a 4k*8 to expand the databus. But on this one I only need to use half of them and the databus length is ...
0
votes
1answer
54 views
What kinds of parallel RAM are there?
I have basically no experience in electrical engineering or hardware design, but as an experienced software engineer, I recently took an interest in designing my own CPU. I followed the ...
0
votes
1answer
137 views
What are the CPU activity steps for the fetch-decode-execute cycle
So in all the phases of the fetch-decode-execute cycle, it says that the "store" phase is used to store any resultant data from the execute phase. What are the CPU steps for that phase? I heard that ...
0
votes
1answer
113 views
How do I convert ldi R17, 129 to machine code
What I got was 1110 1000 0001 0001 when I converted it to machine language. Is that right? Also what are the CPU activity steps and where am I going to use the address 0xF000?
Is this the right CPU ...
3
votes
1answer
108 views
How do wires connect to transistors?
So I was looking at the schematic of NPN and PNP transistors which basically involved layered blocks of doped material stacked.
My question is how do wires connect to these devices? I think this ...
1
vote
1answer
102 views
How does a CPU change frequency? [duplicate]
From what I've found on the internet, CPU clocks work with piezoelectric material to produce a very stable oscillating signal but those materials must change in shape or size to get a different ...
0
votes
1answer
57 views
CPU ports and cache controllers
I have seen CPUs conforming to Harvard architecture with dedicated ports for program memory and data memory. I have also seen that instruction and data caches (read-through caches) are connected to ...
1
vote
2answers
107 views
AND gate with a single input in a diagram
consider the following diagram:
http://ee-classes.usc.edu/ee459/library/datasheets/DM74LS181.pdf
( page 3 )
The first AND gate at the top left of the schematic has only one input! What does this ...
0
votes
2answers
126 views
Does the databus size matter for determining the range of the memory addresses?
If you have byte addressable memory, does it matter if you have a 32 bit or 64 bit databus for the range of the memory addresses for the words of the memory?
E.g.
: Assume a 32-bit word. If you have ...
0
votes
2answers
168 views
When do I call it CPU and when IC-Chip?
Currently I'm a it confused. A IC (integrated Circuit) Chip implements one or many circuits on a chip in order to control any kind of stuff.
However, a CPU is from my point of view also a BIG circuit ...
1
vote
3answers
176 views
How to link ALU to registers, RAM and Clock?
I've designed a basic 4-Bit ALU which computes A+B, A-B, B-A, and a few logic operations. I'm using a mux to determine which output appears at the multiplexer output. This is a basic start to a CPU as ...
0
votes
0answers
68 views
One chip-select/die-termination/clock-enabler for multiple DDR3 DRAM chips
I'm struggling to know how one DRAM chip select pin, DRAM_CS below can help the processor/CPU manage four DRAM chips?
And also how can one clock enabler ...
1
vote
1answer
96 views
Is there a wire (a bus), albeit a very short one, between the CPU and its level-1 cache?
I was wondering what is the specific connection mechanism between the CPU and its level-1 cache so that in practice level-1 cache access time is reduced to match the CPU clock frequency?
Do level-1 ...
0
votes
3answers
121 views
How are alphabetic characters programmed into a computer?
I'm no cs student, I'm a programmer. I have a couple of questions and a few assumptions that I will make here (correct me if I'm wrong please).
From my understanding is that all the sequences of 1 ...
1
vote
1answer
220 views
Powering a 4-Pin stock CPU heatsink fan with an external power supply
I have scoured this website and the rest of the internet looking for a solution to my particular issue, but as of yet I have not found an answer. If this is a duplicate question I am sincerely sorry, ...
3
votes
3answers
277 views
Difference between Micro-Operations in RISC and CISC processors
I've read that the modern Intel processors use the CISC instructions on the top, which are converted into RISC-like simpler instructions in the form of Micro-Operations at the back-end.
So if Intel ...
0
votes
1answer
50 views
ARM architecture and ARM ISA [duplicate]
I am new to world of ARM trying to understand the core concepts been reading forum where ARM architecture and ARM instruction set is used interchangeably. ARM architecture as i understand is a CPU ...
0
votes
1answer
92 views
PS2 or USB keyboard for custom CPU
I have made a CPU on an FPGA board. It works great but I cannot proceed to make a computer with it until I have an input. What use is a computer if it can talk to you, but you cannot talk to it? It ...
0
votes
1answer
83 views
Can MCU ROM and RAM limitations be scaled?
Please note: Although this specific question has to do with the 32-bit ARM SAM3X8E Cortex M3 series, it is really a generic question that should be applicable to all microcontrollers, and therefore ...
4
votes
1answer
91 views
Pull up resistor in NMOS logic value
For my senior high school project I decided to build a basic CPU from discrete components. I plan on using a 5V logic level and the current design calls for around 2000-3000 N-channel MOSFET ...
3
votes
1answer
75 views
Use different footprint for a SATA connector
I am designing an Linux Board which needs a SATA connector.
Now im faced to choose between 2.5 HDD SATA connectors and the new mSATA (mini PCI express) connectors.
For compatiblity and usuabillity ...
2
votes
2answers
264 views
Why does my ALU design delay outputting the results for two clock cycles since input of valid data?
Hello EE StackExchange!
I have been trying to design a simple 8-bit CPU for several months now. However, I am experiencing a problem: The ALU outputs the result of the operation two clock cycles ...
-1
votes
1answer
938 views
How do I build RAM/CPU with logic circuits? [closed]
I want to build a little 4 bit computer, out of logic circuits. I want RAM and a CPU and all that good stuff. My main problem is, should I work on RAM or CPU, which one would "teach" me more so that I ...
