Stands for Very Large Scale Integrated circuits, which at one time had meaning in context to individual logic gates, and MSI (Medium Scale IC - UARTS etc.) with the advent of modern processes with Billions of transistors per design it is used as a generic term to mean IC's in common usage.
0
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1answer
48 views
What will the output of filp-flop if its input is metastable?
I was reading sunburst paper on Clock Domain Crossing and got stuck with this doubt.
Here in the 3rd flip flop, input is metastable state but at the rising edge of the clock output was set to high. ...
0
votes
0answers
35 views
Minimum delay path and sizing of CMOS gates
I've been wracking my brain for the past 3 hours trying to figure this one out, and all the examples I've seen just slap an answer on there like it's supposed to be obvious, which I can't for the ...
0
votes
0answers
13 views
Optimum 1-bit full adder with least PDA product
Out of the following adders which one have the best (Power \$\times\$ Delay \$\times\$ Area) product :
Mirror adder
Complementary Pass Transistor Logic
Dual-rail domino
Transmission gate full adder
...
0
votes
1answer
56 views
Why the pins of a port in some microcontrollers are not in order? [duplicate]
In some ICs the pin numbers are not in proper order. For example, in msp430x12x2 series (following pic).
In the pic, why don't P2.0 be available at pin 20 (or adjacent to P1.0 ??)
Why is that few ...
3
votes
1answer
53 views
Kick-off Spread Spectrum Clocking
Need of SSC:
Spread spectrum clocking (SSC) is a special way to reduce the radiated emissions of digital clock signals. These levels or energy is radiated and therefore this is where a potential EMI ...
0
votes
0answers
20 views
IEEE 754: Rounding in an adder
Now I am trying to build a Floating Point Unit (FPU) using Verilog.
After studying the rounding methods in IEEE 754, I understand that there are three internal bits(G - Guard, R - Round, S - Sticky) ...
1
vote
1answer
22 views
Why diffusions in CMOS CAD tool (Magic) is continuous
I am using Magic to draw some transistors and create digital logic gates. While I was studying the theory about MOSFET I've always seen images like the one below.
In this picture, one can see that ...
2
votes
1answer
50 views
SDC constraints for two flop sychronizer
I have doubt, What should be proper SDC constraint for CDC module, i.e., two flop synchronizer.
between "dat driving by aclk to ...
3
votes
2answers
136 views
What method do you suggest for prototyping asynchronous circuits?
I got surprised and to a degree shocked by finding that there is no proper established tool for designing and prototyping asynchronous circuits.
I keep searching using google and other means to find ...
0
votes
1answer
34 views
Using super-cutoff to reduce Direct Source to Drain Tunnelling
I was wondering if anyone had any insight on how useful it would be to reduce direct source to drain tunnelling by applying negative gate bias voltages on sub-10nm FinFETs. Has anyone looked at this ...
1
vote
2answers
29 views
Transistor level netlist benchmarks
I'm PhD student in CAD/EDA field. My research topic covers VLSI standard cell's layout design and detailed routing. To make my research results more reliable, I would like to test proposed algorithm ...
0
votes
2answers
55 views
impact of removing “+:d” in verilog timing section
I would like to start with the simple example of a flop, and my concentration lies in the specify section , so please ignore the functionality part
...
0
votes
1answer
62 views
Power down current
I'm designing a Variable Gain Amplifier (VGA) for a course project. I'm using Cadence CMOS 180nm technology. One of the requirements is to find the power down current through simulation. I searched on ...
0
votes
1answer
74 views
Inter die vs Intra die process variation
Due to fabrication process, there will be variations, among wafers as well as among dies across a wafer.
My question is that what variations are significant between dies? And what variations are ...
0
votes
1answer
78 views
What is the meaning of Bootstrapping Phenomenon in MOSFET,What are its Consequences & How to avoid it?
According to what i have read from book Bootstrapping occurs because of capacitance b/w Gate & drain of mosfet,Bootstrapping Phenomenon results into Glitches at the output.I have read from ...
1
vote
1answer
109 views
Op-amp - dual to Single supply conversion to avoid floating of input signal?
I'm designing a voltage measurement adaptor. And my signals are PWM type which ranges from 0-36V. I thought of using Op-amp to step down to 0-5V range and use an ADC to convert analog signals into ...
-1
votes
1answer
77 views
Simulating Voltage regulator LM7805 in Cadence Virtuoso
I want to simulate the voltage regulator 7805 in Cadence Virtuoso and for doing so I've downloaded the data sheet for the schematic diagram. As I've intentions to strictly use pmos and nmos from the ...
1
vote
1answer
466 views
Basic TIE HIGH and TIE LOW circuits in Digital VLSI Design
I am trying to understand how a basic TIE HIGH and TIE LOW circuit that are based on diode connected MOSFETs followed by a PMOS pullup or NMOS pull down for TIEHI/TIELO accordingly work ?
How does ...
0
votes
1answer
75 views
What is difference if Floorplanning for FPGA, ASIC (Standard Cell Based) & Gate Array?
Floorplanning is the step, in which functional blocks are allocated on chip area and total chip area, pins location are finalized.
Now what is the difference in Floorplanning for FPGA, ASIC and Gate ...
2
votes
2answers
227 views
First chip with 1000 or more transistors?
I am wondering what was the first chip ever with over 1000 transistors?
I already am aware of the following:
The Intel 4004 was the first commercially available single-chip
microprocessor and it ...
0
votes
1answer
62 views
Clock nets Routing
We know that the clock tree synthesis is performed before signal routing. What is the specific reason for that. Or we can route both at the same time?
0
votes
1answer
56 views
Nesting entities in VHDL (Altera Quartus)
I want to ask a question. I'm trying to simulate a cpu. I did my schema and basically there are two logical parts of the CPU.
The first part is composed of a FIFO buffer, Cache memory for ...
0
votes
1answer
36 views
data bus power consumption
In a design I have, I am using a memory arb (receiving mem requests from two masters) What are the pros and cons for each of the follwing:
use a mux for the read data of each master, so that if the ...
0
votes
1answer
70 views
Complementary Transmission Gate Circuit
Here is the circuit.
Now what would be the voltages at Node Y on the positive edge of the clock, if Switching Time from on to off and off to on of Transmission Gates are : 0.5ns, 1ns, 2ns
2
votes
7answers
1k views
Why are 11, 111, 1111, … equivalent to -1 in two's complement? [duplicate]
According to two's complement, the binary numbers 111 and 11111111 are equivalent to -1. Why or how are the binary numbers 11, 111, 1111, 1111 1111, etc. equivalent to -1 in two's complement? Can ...
4
votes
3answers
324 views
Why All 1's used as a second input in decrement operation of ALU?
Suppose the first four data inputs are X (X0, X1, X2, X3) and the second four data inputs are Y (Y0, Y1, Y2, Y3) in a 4-bit ALU. Why "All 1's" are used as an input for Y in the decrement operation of ...
0
votes
2answers
90 views
MOSFET as a switch. Why does the voltage depend on the gate?
Let's say I have an NMOS, the gate is connected to 5 volts, Vth is 0.7 volts and I want to pass a voltage of 7 using the NMOS as a switch. Can you tell me what will be the voltage at the source?
Will ...
0
votes
2answers
56 views
verilog coding in modelsim
can anyone tell me the verilog coding and simulation for this design using modelsim software..i had tried a lot by the following coding but i can't get the correct result..please i need it for my ...
-1
votes
1answer
1k views
Why inductors can not be integrated into IC? [duplicate]
If passive components like resistor and capacitor can be integrated into an IC, why not inductor?
2
votes
2answers
559 views
What does “+:” mean in Verilog?
When I was looking at someone's Verilog code, I found "+:" in Verilog.
It looks like an arithmetic function but I'm not sure. I never seen before. Does anyone know this usage?
Update:
...
1
vote
4answers
421 views
What is the set in D FF?
I'm trying to implement a 3-bit counter using basic gates (AND, OR, XOR, NOT etc..) around 3 D-type flip-flops. The input is an increment signal that when set to 1 will allow the counter to increment ...
-2
votes
2answers
511 views
What is the timing arc in vlsi?
What is the timing arc? STA and Design compiler.
When I was finding the arc at internet, just it written like this.
Timing arc is the timing of data signal travelling ff to ff.
Is this some kind of ...
-2
votes
4answers
2k views
How do I calculate the maximum frequency?
How could I calculate this questions? Would you please let me know?
Given the above design,reference the figure
1.What are the effective setup and hold times between IN and CLK in the above ...
0
votes
1answer
411 views
How can I calculate max, min frequency between FF to FF in RTL design?
I am trying to review regarding RTL design.
The RTL design as follows
--FF---Comb----FF----FF----
And each FF have same configure like this
setup 1ns
hold 1ns
output 0.5ns
Also, the ...
0
votes
0answers
1k views
Why are END CAP cells required in VLSI Physical Design?
ENDCAP cells are usually placed at the endings of rows. Why are they required ? Why can't we just use FILLER cells ? And what is the structural difference between ENDCAP cells and FILLER cells ?
0
votes
3answers
7k views
PullUp and PullDown Network in CMOS
How exactly pullUp and pullDown Network in CMOS should be defined... I mean why "PullUP" or "PullDown"? And why PMOS in pullUp network and NMos in Pulldown network?Why not Pmos in pullDown and Nmos in ...
0
votes
1answer
119 views
recalculate delay from fsdb file
I came across hsim help menu and I found these two switches pretty interesting.
...
0
votes
1answer
126 views
Blocking and Nonblocking statements in same procedural block
Code
module block;
reg a;
reg b = 1'b0;
reg c = 1'b1;
initial begin
c = b;
a <= c;
end
endmodule
I simulated the code fragment shown in ...
0
votes
1answer
214 views
NAND equal rising and falling time in Spice
I have written a spice code to implement a NAND gate. Then I measured the switch time of that. (The time between change in input which effects the output). I want the rising and falling time to be ...
1
vote
1answer
135 views
adjust clock frequency using Timing Error Avoidance Technique
I am following the next example as is depicted on the diagram, in order to adjust the clock frequency of a multiplier to its maximum.
The System works as follows:
The flip-flop at the input to the ...
0
votes
1answer
155 views
0
votes
1answer
179 views
How to reduce an ALU logic with the minimum logic possible? Its very challenging
Our professor wants us to reduce 8 function alu (8 outputs) to a 4 out ALU that has capability to implement all the 8 functions. We can use any gates(even aoi's), muxes, and can create our control ...
-4
votes
2answers
587 views
I need help with verilog code, I am in trouble?
I am basically setting different control signals for the ALU to perform operations in verilog. But I have tried all possible ways of writing what I want but in vain, can you help me out. How should I ...
7
votes
1answer
332 views
Precise differences between DRAM and CMOS processes
There are a couple of questions that mention the difference between standard CMOS processes and DRAM manufacture:
Why do microcontrollers have so little RAM?
How do they integrate logic into a DRAM ...
1
vote
1answer
78 views
How do you reduce an 8 output ALU to a 4 or 3 output ALU?
I can implement the functions in the picture below, but then if I implement them independently, I would have 8 outputs to the mux. Our professors wants us to reduce the ALU to only 3 or 4 outputs, I ...
1
vote
1answer
181 views
How do you store A or B in a RAM of a CPU datapath?
I have an assignment to make a CPU, but am confused with how f_left and f_right are going to be used. I think they are to store ...
2
votes
1answer
241 views
Free spice Model to simulate integrated circuits design
I am using ltspice and I would like to simulate integrated full custom circuits for educational purpose.
I found the NMOS4 and PMOS4 models but there are not enough since there are too ideal there ...
1
vote
1answer
228 views
NAND gate LVS problems in Cadence Virtuoso
I don't know why my layout won't pass LVS. I am constructing a NAND gate, and it looks like I have all connections in the schematic and layout fine, but I can't get it to say success. What could be ...
1
vote
0answers
72 views
Preference of MOS resistor as load in MOS inverter [closed]
Whys is a MOS resistor preferred over diffused resistor as load in design of a MOS inverter?
-1
votes
2answers
2k views
Understanding Combinational Feedback Loops
1) Please give me a simple example of a verilog code that results in combo feedback loop.
2) Why are these feedback loops undesired in your design? ...
