jbush001 / NyuziProcessor

901

GPGPU microprocessor architecture

fpga gpu-computing gpu verilog hardware microprocessor graphics processor-architecture

Good first issues

Document how to set up LLDB with IDE

documentation

#88 opened about 2 years ago by jbush001

1

C Updated Jul 7, 2019

cyring / CoreFreq

775

CoreFreq is a CPU monitoring software designed for the 64-bits Processors.

C Updated Jul 20, 2019

opcm / pcm

725

Processor Counter Monitor

C++ Updated Jun 19, 2019

mortbopet / Ripes

156

A graphical 5-stage RISC-V pipeline simulator & assembly editor

risc risc-v education simulator qt processor-architecture cpu-emulator computer-architecture

C++ Updated May 21, 2019

hlorenzi / customasm

68

💻 Assembler for custom, user-defined instruction sets! https://hlorenzi.github.io/customasm/web/

Rust Updated Jun 23, 2019

sstsimulator / sst-elements

30

SST Architectural Simulation Components and Libraries

simulator memory processor-architecture networking processor network-analysis cache cache-simulator trace system-design hpc

C++ Updated Jul 19, 2019

sdasgup3 / parallel-processor-design

6

Super scalar Processor design

Verilog Updated Sep 7, 2014

alexander-titov / public

4

A collection of my cources, lectures, articles and presentations

lectures presentations computer-science computer-architecture computer-engineering cpu processor-architecture digital-design

C++ Updated Jun 25, 2019

alirezakay / RISC-CPU

4

A multi cycle RISC CPU (processor) like MIPS CPU in VHDL ( a hardware side code implementation )

cpu cpu-model cpu-architecture processor-design processor-architecture mips-processor isa instruction-set-architecture multi-cycle risc-processor vhdl vhdl-code vhdl-modules

VHDL Updated Jul 13, 2019

phillipstanleymarbell / sunflower-simulator

3

Sunflower Full-System Hardware Emulator and Physical System Simulator for Sensor-Driven Systems. Built-in architectur…

processor-simulator processor-architecture cross-compiler simulator embedded-systems emulators battery-simulator network-simulator power-simulator hitachi superh j-core riscv-simulator riscv-emulator riscv-sim riscv32 riscv

C Updated Jul 17, 2019

zostale / WISC-SP13

2

CS 552 term project : functional design of a microprocessor called the WISC-SP13

verilog verilog-hdl processor-architecture mips-assembly hardware-designs processor cs552

Assembly Updated May 14, 2017

NSU-ACM-SC / 16bit_processor_design

2

hardware-designs logisim simula processor-architecture processor mips-simulator mips mips-assembly mips-processor mips-assembler

Updated Sep 15, 2018

bit0fun / Fusion-Core

2

Open source ISA | Useful in co-processors/CISC add-ons, and limitless code compatibility

processor-architecture multiprocessor verilog verilog-hdl fpga-firmware

Coq Updated Mar 12, 2018

luk3Sky / Building-A-Processor---Project

1

Design of a simulated 8-bit single-cycle processor using Verilog HDL, which includes an ALU, a register file and othe…

verilog-hdl verilog-project processor-architecture hdl alu

Verilog Updated Jan 28, 2019

basebandit / learn-asm

1

This is my little corner where i get to learn assembly and some really low level concepts

assembly-language assembly-language-programming x86 x86-64 processor-architecture ia-32

Updated Oct 11, 2017

maxislash / 8BitProc

1

Implementation of an 8-bit processor on a Xilinx FPGA in VHDL

vhdl fpga nexys4 xilinx processor processor-architecture

VHDL Updated Aug 23, 2017

levindoneto / MIPS

1

Microprocessor without Interlocked Pipeline Stages with the extra JR, DIV and MFLO instructions implemented.

mips processor-architecture instruction-set-architecture monocycle-processor multicycle-processor pipeline-processor

Updated Oct 7, 2016

tilk / sextium-iii-verilog

1

Sextium® III processor implemented in Verilog

verilog processor-architecture fpga altera teaching

Verilog Updated Aug 20, 2018

MarceloFCandido / mult-processor

1

Project of a Verilog implementation of a multicycle processor for the discipline of Computer Architeture and Design II

computer-architecture processor-architecture multicycle-processor

Verilog Updated Mar 26, 2019

phillipstanleymarbell / sunflower-simulator-gui

1

GUI for the Sunflower embedded microarchitectural simulator / full-system emulator.

sunflower-simulator emulator processor-architecture processor-simulator inferno-apps

Limbo Updated Feb 7, 2016

gumienny / 0x0ACE-CPU-solved

1

Let's start short esoteric journey.

isa cpu machine-code assembly-language processor-architecture processor-simulator opcode registers binary-analysis

JavaScript Updated Jul 20, 2017

damieng / binarycpu

Identify the processor architecture of binary files

processor-architecture pefile npm

JavaScript Updated Feb 28, 2018

Subangkar / Computer-Architecture-CSE-306-BUET

Simulation of Designs of Basic Computer & Processor Architecture(4-bit MIPS CPU, Floating Point Adder) in Logisim as …

mips-architecture mips mips-processor floating-point-arithmetic logisim simulation circuit-simulation 4-bit cpu 4-bit-cpu 16-bit-floating-point-adder alu processor-design processor-architecture registers computer-architecture buet cse-buet cse

VHDL Updated Aug 11, 2018

elvircrn / 80085

A microprocessor implemented in VHDL

processor-architecture vhdl xilinx fpga logic-programming

C++ Updated Feb 4, 2017

namangl / RISC-Simulator

SimpleRISC simulator

C++ Updated Oct 23, 2017

eagi223 / Multicycle-Implementation-of-slightly-parallel-processor

UK CS480 - Advanced Computer Architecture : Project 2 - multi-cycle Verilog implementation of loQ Don

verilog processor-architecture

Verilog Updated Apr 4, 2017

levindoneto / Neander

Hipotetic Processor Neander in VHDL.

neander processor-architecture vhdl

VHDL Updated Jan 15, 2017

Plastix / Simple-CPU

Final project from my computer organization class

cpu processor-architecture assembly assembler

Assembly Updated Jun 25, 2018

MarceloFCandido / el-tomasulo

Implementation of Tomasulo's algorithm in Verilog for the Computer Architecture and Design II discipline

hardware processor-architecture tomasulo-algorithm computer-architecture

Stata Updated Mar 26, 2019

BrunoBMoura / BMCORE1

Functional CPU designed in VERILOG HDL inspired on MIPS architecture

mips risc-processor processor-architecture verilog-hdl

Verilog Updated Jun 28, 2019

processor-architecture

Repositories 56

Good first issues