riscv

Here are 230 public repositories matching this topic...

aquynh / capstone

Capstone disassembly/disassembler framework: Core (Arm, Arm64, BPF, EVM, M68K, M680X, MOS65xx, Mips, PPC, RISCV, Sparc, SystemZ, TMS320C64x, Web Assembly, X86, X86_64, XCore) + bindings.

Updated Jul 19, 2020
C

chipsalliance / rocket-chip

Star

Rocket Chip Generator

scala rocket-chip chip-generator chisel riscv rtl

Updated Jul 19, 2020
Scala

rcore-os / rCore

Star

Rust version of THU uCore OS. Linux compatible.

rust mips x86-64 osdev riscv aarch64

Updated Jul 9, 2020
Rust

openhwgroup / cva6

Star

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

asic cpu fpga riscv questasim verilator systemverilog-hdl rv64gc ariane

Updated Jul 17, 2020
SystemVerilog

darklife / darkriscv

Star

opensouce RISC-V implemented from scratch in one night!

fpga riscv rtl verilog risc-v rv32i softcore processor-design rv32e

Updated Jun 19, 2020
Verilog

SpinalHDL / VexRiscv

Star

A FPGA friendly 32 bit RISC-V CPU implementation

cpu fpga vhdl riscv verilog soc spinalhdl softcore

Updated Jul 16, 2020
Assembly

riscv-boom / riscv-boom

Star

SonicBOOM: The Berkeley Out-of-Order Machine

scala berkeley boom rocket-chip chisel riscv rtl riscv-boom

Updated Jul 18, 2020
Scala

rv8-io / rv8

Star

RISC-V simulator for x86-64

linux emulator metadata simulator disassembler histogram riscv isa risc binary-translation macro-op-fusion rv-sys rv-sim rv-meta rv-jit rv8

Updated Jul 10, 2019
C++

openhwgroup / cv32e40p

Star

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

riscv riscv32imfc

Updated Jul 18, 2020
SystemVerilog

pulp-platform / pulp-dronet

Star

A deep learning-powered visual navigation engine to enables autonomous navigation of pocket-size quadrotor - running on PULP

deep-learning cnn artificial-intelligence riscv autonomous-quadcoptor pulp closed-loop-control end-to-end-learning nano-uav

Updated Jan 15, 2020
C

TheThirdOne / rars

Star

RARS -- RISC-V Assembler and Runtime Simulator

education simulator ide assembler riscv mars risc risc-v rarr scavenger-hunt mars-xray runtime-simulator

Updated Jul 15, 2020
Java

syntacore / scr1

Star

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

core riscv rtl ip verilog risc-v rv32i rv32e rv32imc rv32emc

Updated Jul 16, 2020
SystemVerilog

f32c / f32c

Star

A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz

arduino fpga mips riscv xilinx altera lattice

Updated Jul 1, 2020
VHDL

sergeykhbr / riscv_vhdl

Star

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

debugger qt simulator cpu vhdl riscv systemc soc

Updated Jul 16, 2020
C++

ucb-bar / chipyard

Star

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

boom rocket rocket-chip chip-generator chisel riscv rtl peripherals soc out-of-order superscalar risc-v firesim accelerators chipyard hwacha

Updated Jul 19, 2020
C

larsbrinkhoff / lbForth

Star

Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.

linux programming-language avr arm interpreter cortex-m compiler self-hosted riscv forth x86 msp430 pdp11 metacompiler m68k asmjs 6502 risc-v 8051

Updated Sep 17, 2019
Forth

andrescv / Jupiter

Star

RISC-V Assembler and Runtime Simulator

education simulator assembler riscv risc risc-v riscv-asm rv32 rv32imf riscv-simulator runtime-simulator

Updated Oct 29, 2019
Java

beehive-lab / Maxine-VM

Star

Maxine VM: A meta-circular research VM

java research jvm riscv x86 armv7 graal aarch64 risc-v metacircular-vm c1x t1x maxine-vm

Updated Jul 16, 2020
Java

chipsalliance / Cores-SweRV

Star

SweRV EH1 core

fpga processor riscv rtl risc risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design swerv swerv-eh1

Updated Jul 6, 2020
SystemVerilog

ucb-bar / riscv-mini

Star

Simple RISC-V 3-stage Pipeline in Chisel

chisel riscv rtl

Updated Mar 12, 2020
Scala

nervosnetwork / ckb-vm

Star

CKB's vm, based on open source RISC-V ISA

rust blockchain riscv ckb smart-contract nervos

Updated Jun 23, 2020
Rust

takahirox / riscv-rust

Star

RISC-V processor emulator written in Rust+WASM

emulator rust cpu processor webassembly wasm riscv risc-v

Updated Jul 2, 2020
Rust

mrLSD / riscv-fs

Star

F# RISC-V Instruction Set formal specification

library cpu fsharp fs riscv isa risc-v risc-processor riscv32 riscv64 riscv-simulator riscv-emulator

Updated Jul 7, 2020
F#

windelbouwman / ppci

Star

A compiler for ARM, X86, MSP430, xtensa and more implemented in pure Python

python arm compiler x86-64 assembler webassembly riscv msp430 c-compiler c-preprocessor m68k xtensa

Updated Jul 12, 2020
Python

bu-icsg / dana

Star

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

neural-network hardware rocket-chip chisel riscv rtl rocc

Updated Jan 23, 2020
Scala

riscv / meta-riscv

Star

OpenEmbedded/Yocto layer for RISC-V Architecture

riscv yocto-layer yocto openembedded risc-v yocto-meta openembedded-layer

Updated Jul 17, 2020
BitBake

l919898756 / RISC-V_article_paper_src

Star

riscv资料、论文等

riscv

Updated Oct 24, 2018
HTML

diodesign / diosix

Star

A lightweight, secure, multiprocessor bare-metal hypervisor written in Rust for RISC-V

rust kernel hypervisor riscv microkernel risc-v diosix

Updated Jun 8, 2020
Rust

Domipheus / RPU

Star

Basic RISC-V CPU implementation in VHDL.

cpu fpga vhdl riscv risc-v apache2-license

Updated May 17, 2020
VHDL

scarv / xcrypto

Star

XCrypto: a cryptographic ISE for RISC-V

open-source cryptography cpu crypto hardware riscv verilog research-project mit-license ise icarus-verilog hardware-acceleration formal-verification yosys instruction-set-architecture risc-v xcrypto

Updated Jul 17, 2020
Verilog

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