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risc

Here are 170 public repositories matching this topic...

Ripes

mortbopet / Ripes

Sponsor Star

A graphical processor simulator and assembly editor for the RISC-V ISA

education processor-architecture qt simulator computer-architecture risc risc-v cpu-emulator

Updated Jul 21, 2021
C++

michaeljclark / rv8

Star

RISC-V simulator for x86-64

linux emulator metadata simulator disassembler histogram riscv isa risc binary-translation macro-op-fusion rv-sys rv-sim rv-meta rv-jit rv8

Updated May 31, 2021
C++

chipsalliance / Cores-SweRV

Star

SweRV EH1 core

fpga processor riscv rtl risc risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design swerv swerv-eh1

Updated Mar 12, 2021
SystemVerilog

Jupiter

andrescv / Jupiter

Star

RISC-V Assembler and Runtime Simulator

education simulator assembler riscv risc risc-v riscv-asm rv32 rv32imf riscv-simulator runtime-simulator

Updated Jul 25, 2020
Java

mipt-mips

MIPT-ILab / mipt-mips

Star

Open

Verify correctness of read-after-write behavior

pavelkryukov commented Mar 18, 2020

Some RISC-V instructions perform writes to 2 destinations, either 2 register or register or program counter. In cases if the source of one sub-operation matches a destination of another one, the order of result output is important. The examples are jalr and instruction operating with CSRs:

riscv/riscv-tests#258
riscv/riscv-tests#263

Your obj

Read more

1 S1 — ISA good first issue testing

Open

Implement RV64 bit manipulation instructions on 32-bit registers

Open

Implement remaining RISC-V B instructions

Find more good first issues →

LekKit / RVVM

Star

RISC-V Virtual Machine

c emulator vm virtual-machine emulation riscv risc emulators risc-v riscv32 riscv-emulator instruction-decoding rvvm

Updated Jul 24, 2021
C

Wren6991 / RISCBoy

Star

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

cpu fpga gameboy pcb risc risc-v

Updated Apr 11, 2021
C

kvakil / venus

Star

RISC-V instruction set simulator built for education

education frontend backend assembler risc risc-v venus

Updated Jan 5, 2019
Kotlin

Vulcan

vmmc2 / Vulcan

Star

RISC-V Instruction Set Simulator (Built for education).

education simulator assembly computer-architecture risc risc-v

Updated Jul 15, 2021
Dart

mrisc32

mrisc32 / mrisc32

Star

MRSIC32 ISA documentation and development

cpu isa risc mrisc32

Updated Jul 20, 2021
TeX

Mariotti94 / WebRISC-V

Star

WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]

php education processor-architecture simulator pipeline assembly computer-architecture risc risc-v pipeline-simulation-environment

Updated Feb 23, 2021
PHP

liuqidev / 8-bits-RISC-CPU-Verilog

Star

Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。

cpu fsm verilog risc

Updated Jan 20, 2019
Verilog

lxp32 / lxp32-cpu

Star

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

cpu fpga vhdl risc wishbone soft-core risc-processor wishbone-bus risc-cpu

Updated Feb 25, 2019
Assembly

michaeljclark / riscv-meta

Star

RISC-V Instruction Set Metadata

metadata riscv risc risc-v

Updated Oct 21, 2018

SuperJMN / Plotty

Sponsor Star

C language compiler from scratch for a custom architecture, with virtual machine and all

c emulator parser csharp parsing compiler uwp virtual-machine net risc c-language superpower

Updated May 13, 2018
C#

wel97459 / FPGACosmacELF

Star

A re-creation of a Cosmac ELF computer, Coded in SpinalHDL

cpu fpga processor fred risc rca 8bit spinalhdl cosmac cosmac-elf

Updated Apr 23, 2021
VHDL

ustb-owl / Uranus

Star

Uranus MIPS processor by MaxXing & USTB NSCSCC team

cpu fpga mips verilog risc

Updated Dec 14, 2019
Verilog

bitmario / RISVM

Star

A low overhead, embeddable bytecode virtual machine in C++

vm interpreter bytecode cpp virtual-machine asm assembler risc bytecode-interpreter

Updated Dec 25, 2018
C++

mrisc32 / mrisc32-a1

Star

A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA

cpu vhdl risc soft-core fpu mrisc32

Updated Jul 20, 2021
VHDL

platformio / platform-shakti

Star

Shakti: development platform for PlatformIO

platformio riscv risc risc-v platformio-platform

Updated Jan 28, 2021
Python

ulx3s / ulx3s.github.io

Star

community projects that can be used with the ULX3S FPGA ESP32 board

fpga vhdl verilog risc ecp5 ulx3s emard

Updated Oct 16, 2020

lite-david / comet

Star

RISC-V ISA based 32-bit processor written in HLS

asic fpga hls comet isa vivado risc catapult

Updated Nov 7, 2019
C

pmetras / nim0

Star

Nim0 is a toy compiler for a limited subset of Nim language, all in 5 heavily documented source files so that you can understand them. It is a port of Niklaus Wirth's Oberon-0 compiler.

emulator nim compiler toy-language risc oberon0

Updated Apr 27, 2021
Nim

BigEd / XSOC-xr16

Star

System-on-a-Chip for FPGA, with xr16 RISC core and LCC port

cpu fpga risc system-on-chip 16bit non-commercial-license revocable-license

Updated Jul 23, 2017
C

rv-link

michahoiting / rv-link

Star

RV-Link: In application debugger for RISC-V micro-controllers, RISC-V emulator, running on RISC-V development boards (e.g. Sipeed Longan Nano or GD32VF103C-START).

c microcontrollers platformio risc jtag dongle jtag-probe longan-nano gd32vf103 rv-link

Updated Feb 10, 2021
C

dominiksalvet / risc63

Star

💻 Custom 64-bit pipelined RISC processor.

Updated Jan 6, 2021
VHDL

SoCXin / RISC-V

Star

RISC-V architecture

architecture risc

Updated Jan 9, 2021

ben-marshall / croyde-riscv

Star

A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.

cryptography microcontroller cpu crypto verilog mit-license systemverilog risc formal-verification yosys risc-v verilator micro-controller riscv64

Updated Feb 25, 2021
SystemVerilog

CSopiko / ASMulator

Star

Assembly Virtual Machine Emulator implemented in C++ for Programming Paradigms course (Free university of Tbilisi) bonus assignment.

emulator cpp virtual-machine assembly asm risc

Updated Feb 28, 2021
C++

KPU-RISC / KPU

Star

KPU - the RISC based Open Source CPU

cpu compiler assembler osdev risc cpu-emulator

Updated Nov 4, 2017
C#

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