Here are
51 public repositories
matching this topic...
Teaching Materials for Dr. Waleed A. Yousef
Updated
Mar 29, 2021
Mathematica
Automatically interpret and validate nested natural logic arguments based on rules of inference and propositional logic
Updated
Jun 6, 2018
Python
EventNext is logic interface design actors components for .net core
Circuit Builder Desktop Application (like mmlogic) made with Electron + React Typescript. Compatible with Windows, Mac and Linux.
Updated
May 10, 2021
TypeScript
All the homeworks, studies and projects I've done at Metu-CENG
Updated
Feb 7, 2021
Jupyter Notebook
Logic Minimization in Python
Updated
Jul 28, 2021
Python
All the homeworks, testers and projects done at METU-CENG
Updated
Apr 27, 2018
Jupyter Notebook
SystemVerilog examples for Digital Design course
Updated
Mar 30, 2021
SystemVerilog
ELVE : ELVE Logic Visualization Engine
A collection of digital logic circuits
Updated
Sep 24, 2020
SystemVerilog
Automated conversion from CHP to PRS using syntax-directed translation
Updated
Jul 23, 2021
Perl
Updated
May 19, 2021
Swift
A place for my asynchronous logic code
Updated
Feb 22, 2019
VHDL
All the homeworks, testers and projects done at Marmara University, Computer Science & Engineering
Updated
Feb 17, 2021
Java
Boolean expression simplifier and visualizer
Updated
Apr 22, 2017
Java
University of Marmara, CSE3015 2018 Fall Project
Updated
May 14, 2019
Java
Updated
Apr 4, 2017
Verilog
16 bit MIPS microprocessor on CircuitSim
This repository holds .hdl files that modularly describes the Hack hardware platform.
Updated
Jul 16, 2021
Scilab
Two's complement two bit multiplier developed in Proteus
Includes some assignments/reports belonging to the courses attended during my BSc degree.
Updated
Sep 8, 2018
MATLAB
A digital design for the SPI protocol, delivered as a project for the logic design course
Updated
May 14, 2021
Verilog
🚀 🏞️ A complete village Scenarry with C graphics. 🏕️ 🏝️
Basic Operations of a Processor in Xilinx
Updated
Nov 9, 2019
Verilog
COEN 921C Introduction to Logic Design, Carl Fussell, Santa Clara University
! NOT A HTML PROJECT! / It is a VHDL(VHSIC Hardware Description Language) project for making a 'Taxi Meter Calibrator' which will be implemented on FPGA board system.
Updated
Mar 31, 2020
HTML
Using a linear feedback shift register (LFSR), design a pseudorandom binary sequence (PRBS) generator.
Updated
Aug 9, 2020
Verilog
A circuit simulator in HTML5 and JavaScript
Updated
May 6, 2020
JavaScript
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